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advance data sheet BCM5238 5238-ds03-405-r 16215 alton parkway ? p.o. box 57013 irvine, california 92619-7013 phone: 949-450-8700 fax: 949-450-8710 1/31/03 10/100base-tx octal- ? transceiver figure 1: functional block diagram g eneral description f eatures the BCM5238 is an octal 10/100base-tx transceiver for fast ethernet switches. the device contains eight full- duplex 10base-t/100base-tx fast ethernet transceivers, each of which performs all of the physical layer interface functions for 10base-t ethernet on category 3, 4 or 5 unshielded twisted-pair (utp) cable and 100base-tx fast ethernet on category 5 utp cable. pseudo-100base-fx mode is supported through external fiber-optic tranceivers. the BCM5238 is a highly integrated solution using 0.18- micron technology, combining digital adaptive equalizers, adcs, phase locked loops, line drivers, encoders, decoders and all the required support circuitry into a single monolithic cmos chip. the BCM5238 complies with the ieee 802.3 specification, including the auto-negotiation subsections. the BCM5238 design results in robust performance over a broad range of operating scenarios. problems inherent to mixed-signal implementations, such as analog offset and on-chip noise, are eliminated by employing field- proven digital adaptive equalization and digital clock recovery techniques. 10base-t/100base-tx ieee 802.3u compliant single-chip octal physical interface?smii to magnetics option?source synchronous smii (sssmii) fully integrated digital adaptive equalizers 125-mhz clock generator and timing recovery on-chip multimode transmit waveshaping edge-rate control eliminates external filters hp auto-mdix cable length indication cable noise level indication ieee 802.3u-compliant auto-negotiation shared mii management interface up to 25 mbps programmable serial led pins programmable parallel led pins interrupt output capability loopback mode for diagnostics ieee 1149.1 (jtag) and nand-chain ict support low-power dual-supply 2.5v/1.8v cmos technology compatible with 3.3 v i/o 128 mqfp and 256-pin fbga package a pplications fast ethernet switches mii mii equalizer auto-negotiation led/int clock bias registers mgmt control correction /link integrity generator generator wander baseline 8 rxd{1:8} mdc mdio modes/controls td {1:8} rd {1:8} ref_clk recovery xmt dac crs/link detection adc led2{1:8} sssmii_dis/sled_clk multimode jtag test logic 5 jtag digital adaptive 10base-t pcs 100base-x pcs drivers clock 13 8 intr/sled_do led1{1:8} 8 8 txd{1:8} rdac ssync sssmii_txc sssmii_rsync auto mdix sssmii_rxc
broadcom corporation p.o. box 57013 16215 alton parkway irvine, california 92619-7013 ? 2003 by broadcom corporation all rights reserved printed in the u.s.a. broadcom ? and the pulse logo are registered trademarks of bro adcom corporation and/or its subsidiaries in the united states and certain other countries. all other tra demarks are the property of their respective owners. this data sheet (including, without limitation, the broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high risk application. broadcom provides this data sheet "as- is", without warranty of any kind. broadcom disclaims all warranties, expressed and implied, including, without limitation, the im plied warranties of merchantability, fitness for a particular purpose, and non-infringement. r evision history revision date change description 5238-ds03-405-r 1/31/03 initial release.
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r page i t able of c ontents section 1: functional description ...................................................................................... 1 overview ............................................................................................................................... ........................ 1 encoder/decoder ............................................................................................................................... ......... 1 link monitor ............................................................................................................................... .................. 2 carrier sense ............................................................................................................................... ................ 2 auto-negotiation ............................................................................................................................... .......... 3 digital adaptive equalizer .......................................................................................................................... 3 adc ............................................................................................................................... ................................ 3 digital clock recovery/generator ............................................................................................................... 3 multimode transmit dac ............................................................................................................................ 4 stream cipher ............................................................................................................................... ................ 4 mii management ............................................................................................................................... ............ 4 smii interface ............................................................................................................................... ................. 4 source synchronous smii (sssmii) interface ........................................................................................... 5 interrupt mode ............................................................................................................................... ............... 5 section 2: hardware signal definition table ..................................................................... 7 section 3: pinout diagram ................................................................................................14 section 4: operational description ..................................................................................16 resetting the BCM5238 ............................................................................................................................. 16 phy address ............................................................................................................................... ............... 16 loopback mode ............................................................................................................................... ........... 16 full-duplex mode ............................................................................................................................... ......... 16 10base-t mode ............................................................................................................................... .......... 17 isolate mode ............................................................................................................................... ................ 17 super isolate mode ............................................................................................................................... ..... 17 auto power-down mode ............................................................................................................................ 17 jumbo packet mode ............................................................................................................................... ... 17 section 5: led display output modes ............................................................................. 19 description ............................................................................................................................... .................. 19 serial led mode ............................................................................................................................... .......... 19
BCM5238 advance data sheet 1/31/03 broadcom corporation page ii document 5238-ds03-405-r extended parallel led mode .....................................................................................................................23 transmit and receive led behavior ........................................................................................................24 transmit led................................................................................................................... ......................24 receive led.................................................................................................................... ......................24 section 6: register summary .......................................................................................... 25 mii management interface: register programming .................................................................................25 mii register map summary....................................................................................................... ............26 mii status register ............................................................................................................................... ......31 phy identifier registers .............................................................................................................................32 auto-negotiation advertisement register ...............................................................................................33 100base-x auxiliary control register .....................................................................................................37 100base-x auxiliary status register .......................................................................................................39 100base-x receive error counter ..........................................................................................................40 100base-x false carrier sense counter ................................................................................................40 auxiliary control/status register .............................................................................................................41 10base-t auxiliary error and general status register .........................................................................46 auxiliary mode register .............................................................................................................................47 auxiliary multiple phy register ................................................................................................................48 broadcom test register ............................................................................................................................49 auxiliary mode 4 (phy 1 of 8) register (shadow register) ....................................................................50 auxiliary mode 4 (phy 2 of 8) register (shadow register) ....................................................................50 auxiliary mode 4 (phy 3 of 8) register (shadow register) ....................................................................51 auxiliary mode 4 (phy 5 of 8) register (shadow register) ....................................................................52 auxiliary mode 4 (phy 7 of 8) register (shadow register) ....................................................................53 auxiliary status 2 register (shadow register) ........................................................................................54 auxiliary status 3 register (shadow register) ........................................................................................55 auxiliary status 4 register (shadow register) ........................................................................................56
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r page iii section 7: timing and ac characteristics ...................................................................... 57 section 8: electrical characteristics ................................................................................ 60 section 9: mechanical information ................................................................................... 62 section 10: packaging thermal characteristics ............................................................. 64 section 11: application examples ................................................................................... 65 section 12: ordering information ..................................................................................... 67
BCM5238 advance data sheet 1/31/03 broadcom corporation page iv document 5238-ds03-r l ist of f igures figure 1: functional block diagram ............................................................................................. ........................ i figure 2: BCM5238u pin diagram ................................................................................................. ..................14 figure 3: BCM5238b pin diagram................................................................................................. ...................15 figure 4: clock and reset timing............................................................................................... ......................57 figure 5: smii timing.......................................................................................................... ..............................58 figure 6: management interface timing .......................................................................................... .................59 figure 7: management interface timing (with preamble suppression on) .......................................................59 figure 8: 128-pin mqfp, rev. b................................................................................................. ......................62 figure 9: 256-pin fbga, rev. a ................................................................................................. ......................63 figure 10: smii application .................................................................................................... ...........................65 figure 11: smii application using source synchronous signals................................................................... ...65 figure 12: switch application.................................................................................................. ..........................66
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r page v l ist of t ables table 1: 4b5b encoding ......................................................................................................... ............................ 1 table 2: pin definitions....................................................................................................... ................................ 7 table 3: receive fifo size select .............................................................................................. .................... 18 table 4: jumbo packet enable and descrambler lock timer ........................................................................ ..... 18 table 5: serial led mode bit framing ........................................................................................... .................. 19 table 6: serial mode bank 1 led selection ...................................................................................... .............. 20 table 7: serial mode bank 2 led selection ...................................................................................... .............. 20 table 8: serial mode bank 3 led selection ...................................................................................... .............. 21 table 9: serial mode bank 4 led selection ...................................................................................... .............. 21 table 10: serial mode bank 5 led selection ..................................................................................... ............. 22 table 11: serial mode bank 6 led selection ..................................................................................... ............. 22 table 12: parallel led mode led1 selection..................................................................................... ............. 23 table 13: parallel led mode led2 selection..................................................................................... ............. 23 table 14: extended parallel led selection...................................................................................... ................ 24 table 15: mii management frame format .......................................................................................... ............... 25 table 16: mii register map summary............................................................................................. ................. 27 table 17: mii shadow register map summary (mii register 1fh, bit7 = 1) .................................................... 29 table 18: mii control register (address 00d, 00h) .............................................................................. ............. 30 table 19: mii status register (address 01d, 01h)............................................................................... .............. 31 table 20: phy identifier registers (addresses 02d and 03d, 02h and 03h).................................................... 32 table 21: auto-negotiation advertisement register (address 04d, 04h)......................................................... 33 table 22: auto-negotiation link partner ability register (address 05d, 05h) .................................................. 34 table 23: auto-negotiation expansion register (address 06d, 06h ................................................................ 35 table 24: next page transmit register (address 07d, 07h)....................................................................... ..... 36 table 25: next page transmit register (address 08d, 08h)....................................................................... ..... 37 table 26: 100-base-x auxiliary control register (address 16d, 10h) ............................................................. 37 table 27: 100base-x auxiliary status register (address 17d, 11h)............................................................... 39 table 28: 100base-x receive error counter (address 18d, 12h) .................................................................. 4 0 table 29: 100base-x false carrier sense counter (address 19d, 13h) ........................................................ 40 table 30: 100base-x disconnect counter (address 20d, 14h) ...................................................................... 41 table 31: auxiliary control/status register (address 24d, 18h) ................................................................. ..... 41 table 32: auxiliary status summary register (address 25d, 19h) ................................................................. .43
BCM5238 advance data sheet 1/31/03 broadcom corporation page vi document 5238-ds03-405-r table 33: interrupt register (address 26d, 1ah) ................................................................................ ..............44 table 34: auxiliary mode 2 register (address 27d, 1bh) ......................................................................... ........45 table 35: 10base-t auxiliary error and general status register (address 28d, 1ch) ...................................46 table 36: auxiliary mode register (address 29d, 1dh) ........................................................................... .........47 table 37: auxiliary multiple phy register (address 30d, 1eh) ................................................................... .....48 table 38: broadcom test register (address 31d, 1fh) ............................................................................ .......49 table 39: auxiliary mode 4 (phy 1 of 8) register (shadow register 26d, 1ah) ..............................................50 table 40: auxiliary mode 4 (phy 2 of 8) register (shadow register 26d, 1ah) ..............................................50 table 41: auxiliary mode 4 (phy 3 of 8) register (shadow register 26d, 1ah) ..............................................51 table 42: auxiliary mode 4 (phy 4 of 8) register (shadow register 26d, 1ah) ..............................................52 table 43: auxiliary mode 4 (phy 5 of 8) register (shadow register 26d, 1ah) ..............................................52 table 44: auxiliary mode 4 (phy 6 of 8) register (shadow register 26d, 1ah) ..............................................53 table 45: auxiliary mode 4 (phy 7 of 8) register (shadow register 26d, 1ah) ..............................................53 table 46: auxiliary mode 4 (phy 8 of 8) register (shadow register 26d, 1ah) ..............................................54 table 47: auxiliary status 2 register (shadow register 27d, 1bh)............................................................... ...54 table 48: 100-tx port cable length ............................................................................................. ...................54 table 49: auxiliary status 3 register (shadow register 28d, 1ch)............................................................... ...55 table 50: auxiliary mode 3 register (shadow register 29d, 1dh)................................................................. ..56 table 51: current receive fifo size ............................................................................................ ...................56 table 52: auxiliary status 4 register (shadow register 30d, 1eh)............................................................... ...56 table 53: clock timing ......................................................................................................... ............................57 table 54: reset timing ......................................................................................................... ............................57 table 55: smii timing .......................................................................................................... .............................58 table 56: auto-negotiation timing .............................................................................................. ......................58 table 57: led timing ........................................................................................................... ............................58 table 58: mii management data interface timing ................................................................................. ...........58 table 59: absolute maximum ratings ............................................................................................. .................60 table 60: recommended operating conditions ..................................................................................... ..........60 table 61: electrical characteristics........................................................................................... ........................60 table 62: thetaj a vs. airflow for the BCM5238b package ..............................................................................64 table 63: thetaj a vs. airflow for the BCM5238u package ..............................................................................64
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r functional description page 1 section 1: functional description o verview the BCM5238 is a single-chip device containing eight independent fast ethernet transceivers. each transceiver performs all of the physical layer interface functions for 100base-tx fu ll-duplex or half-duplex ethernet on category 5 twisted-pair cable and 10base-t full-duplex or half-duplex ethernet on category 3, 4, or 5 cable. the chip performs 4b5b, mlt3, nrzi, and manchester enco ding and decoding, clock and data recovery, stream cipher scrambling/descrambling, digital adaptive equalization, line transmission, carrier sense and link integrity monitor, auto-negotiation smii and ssmii management functions. the BCM5238 may be connected to a mac through the smii or ssmii on one side and connects directly to the network medi a on the other side through isolation transformers. the BCM5238 is compliant with the ieee 802.3 standard. e ncoder /d ecoder the BCM5238 transmits and receives a continuous data stream on twisted pair. when the transmit enable is asserted, data from the transmit data pins is encoded into 5-bit code-groups and inserted into the transmit data stream. the 4b5b encoding is shown in table 1 . the transmit packet is encapsulated by replacing the first two nibbles of preamble with a start of stream delimiter (j/k codes) and appending an end of stream delimiter (t/r codes) to the end of the packet. the transmitter repeatedly sends the idle code group between packets. the encoded data stream is scrambled by a stream cipher block and then serialized and encoded into mlt3 signal levels. a multimode transmit dac is used to drive the mlt3 data onto the twisted pair cable. following adaptive equalization, and clock recovery, the receive data stream is converted from mlt3 to serial nrz data. the nrz data is descrambled by the stream cipher block and then deserialized and aligned into 5-bit code groups. the 5-bit code groups are decoded into 4-bit data nibbles, as shown in table 1. the start of stream delimiter is replaced with preamble nibbles and the end of stream delimiter and idle codes are replaced with all zeros. the decoded data is driven onto the smii receive data stream. when an invalid code group is detected in the data stream, the BCM5238 asserts the smii rxer signal in the receive data stream. the chip also asserts rxer for several other error conditions which improperly terminate the data stream. in 10base-t mode, manchester encoding and decoding is pe rformed on the data stream. the multimode transmit dac performs pre-equalization for 100 meters of category 3 cable. table 1: 4b5b encoding name 4b code 5b code meaning 0 0000 11110 data 0 1 0001 01001 data 1 2 0010 10100 data 2 3 0011 10101 data 3 4 0100 01010 data 4
BCM5238 advance data sheet 1/31/03 broadcom corporation page 2 link monitor document 5238-ds03-405-r l ink m onitor in 100base-tx mode, receive signal energy is detected by monitoring the receive pair for transitions in the signal level. signal levels are qualified using squelch detect circuits. when no signal or certain invalid signals are detected on the receiv e pair, the link monitor enters and remains in the link fail state where only idle codes are transmitted. when a valid signal is detected on the receive pair for a minimum period of time, the link monitor enters the link pass state and the transmit and receive functions are enabled. in 10base-t mode, a link-pulse detection circuit constantly monitors the rd pins for the presence of valid link pulses. c arrier s ense in dte mode, the carrier sense and receive data valid signals are multiplexed on the same pin. the carrier sense is asserted asynchronously on crs_dv as soon as valid activity is detected in the receive data stream. loss of carrier shall result in 5 0101 01011 data 5 6 0110 01110 data 6 7 0111 01111 data 7 8 1000 10010 data 8 9 1001 10011 data 9 a 1010 10110 data a b 1011 10111 data b c 1100 11010 data c d 1101 11011 data d e 1110 11100 data e f 1111 11101 data f i 0000 a 11111 idle j 0101 a 11000 start-of-stream delimiter, part 1 k 0101 a 10001 start-of-stream delimiter, part 2 t 0000 a 01101 end-of-stream delimiter, part 1 r 0000 a 00111 end-of-stream delimiter, part 2 h 1000 00100 transmit error (used to force signalling errors) v 0111 00000 invalid code v 0111 00001 invalid code v 0111 00010 invalid code v 0111 00011 invalid code v 0111 00101 invalid code v 0111 00110 invalid code v 0111 01000 invalid code v 0111 01100 invalid code v 0111 10000 invalid code v 0111 11001 invalid code a. treated as invalid code (mapped to 0111) when received in data field. table 1: 4b5b encoding (cont.) name 4b code 5b code meaning
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r auto-negotiation page 3 the deassertion of crs_dv synchronous to the cycle of ref_clk which presents the first di-bit of a nibble onto rxd. if the phy has additional bits to be presented on rxd following the initial deassertion of crs_dv, then the phy shall assert crs_dv on cycles of ref_clk which present the second di-bit of each nibble and deassert crs_dv on cycles of ref_clk which present the first di-bit of each nibble. if carrier sense is asserted and a valid ssd is not detected immediately, then rxer is asserted. a value of 2h (2 hex) is driven on the receive data pins to indicate false carrier sense. in 10base-t mode, carrier sense is asserted asynchronously on the crs pin when valid preamble activity is detected on the rd+/- input pins. a uto - negotiation the BCM5238 can negotiate its mode of operation over the twisted pair link using the auto-negotiation mechanism defined in the ieee 802.3u specification. auto-negotiation is enabled or disabled by hardware or software control. when the auto- negotiation function is enabled, the BCM5238 automatically chooses its mode of operation by advertising its abilities and comparing them with those received from its link partner. the BCM5238 can be configured to advertise 100base-tx full- duplex and/or half-duplex and 10base-t full-duplex and/or half-duplex. each transceiver negotiates independently with its link partner, and chooses the highest level of operation available for its own link. d igital a daptive e qualizer the digital adaptive equalizer removes interzonal interference created by the transmission channel media. the equalizer accepts sampled unequalized data from the adc on each channel and produces equalized data. the BCM5238 achieves an optimum signal to noise ratio by using a combination of feed forward equalization and decision feedback equalization. this powerful technique achieves a 100base-tx ber of less than 1 10 -12 for transmission up to 100 meters on cat 5 twisted pair cable, even in harsh noise environments. the digital adaptive equalizers in the BCM5238 achieve performance close to theoretical limits. the all-digital nature of the design makes the performance very tolerant to on-chip noise. the fil ter coefficients are self adapting to any quality of cable or ca ble length. due to transmit pre-equalization in 10base-t mode, the adaptive equalizer is bypassed in this mode of operation. adc each receive channel has its 125-mhz analog to digital converter (adc). the adc samples the incoming data on the receive channel and produces a digital output. the output of the adc is fed to the digital adaptive equalizer. advanced analog circuit techniques achieve low offset, high power supply noise rejection, fast settling time, and low bit error rate. d igital c lock r ecovery / generator the all-digital clock recovery and generator block creates all internal transmit and receive clocks. the transmit clocks are locked to the 50-mhz clock input while the receive clocks are locked to the incoming data streams. clock recovery circuits optimized to mlt3, nrzi, and manchester encoding schemes are included for use with each of the three different operating
BCM5238 advance data sheet 1/31/03 broadcom corporation page 4 multimode transmit dac document 5238-ds03-405-r modes. the input data streams are sampled by the recovered clock from each port and fed synchronously to the respective digital adaptive equalizer. m ultimode t ransmit dac the multimode transmit digital to analog converter (dac) transmits mlt3-coded symbols in 100base-tx mode and manchester-coded symbols in 10base-t mode. it performs programmable edge-rate control in tx mode, which decreases unwanted high-frequency signal components, thus reducing emi. high-frequency pre-emphasis is performed in 10base-t mode. the transmit dac uses a current drive output that is well balanced and produces very low noise transmit signals. s tream c ipher in 100base-tx mode, the transmit data stream is scrambled in order to reduce radiated emissions on the twisted pair cable. the data is scrambled by exclusive oring the nrz signal with the output of an 11-bit-wide linear feedback shift register (lfsr), which produces a 2047-bit non-repeating sequence. the scrambler reduces peak emissions by randomly spreading the signal energy over the transmit frequency range, and elim inating peaks at certain frequencies. signal energy is spread further by using unique seeds to generate a different non-repeating sequence for each of the eight ports. the receiver descrambles the incoming data stream by ex clusive oring it with the same sequence generated at the transmitter. the descrambler detects the state of the transmit lfsr by looking for a sequence representing consecutive idle codes. the descrambler locks to the scrambler state after detecting a sufficient number of consecutive idle code-groups. the receiver does not attempt to decode the data stream unless the descrambler is locked. once locked, the descrambler continuously monitors the data stream to make sure that it has not lost synchronization. the receive data stream is expected to contain inter-packet idle periods. if the descr ambler does not detect enough idle codes within 724 s, it becomes unlocked, and the receive decoder is disabled. if the receiver is put into token ring mode (see bit 10, register 1bh), the descrambler monitors the receiver for 5792 s before unlocking. the descrambler is always forced into the unlocked state when a link failure condition is detected. stream cipher scrambling/descrambling is not used in 10base-t mode. mii m anagement management of each transceiver within the BCM5238 remains the same as it was under the mii specification. each phy contains an independent set of mii management registers. they share a single mdc/mdio serial interface. each transceiver has a unique address and must be accessed individually. the common base address for the group of eight individual transceivers is defined by configuring the five external phyad address input pins. smii i nterface the objective of this interface is to reduce the number of pins required to interconnect the mac and the phy. this is accomplished by clocking data and control signals in and out of each phy on a pair of pins at a rate of 125 mhz.
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r source synchronous smii (sssmii) interface page 5 data and control signals passing from the mac to the phy use the serial transmit (stx) line; data and control signals passing from the phy to the mac use the serial receive (srxd) line. all bit transfers are synchronous with clock (sclk) at 125 mhz; frame sync is provided by a fourth line (sync), assert ed at the beginning of each frame, which occurs every ten cycles of ref_clk. each phy is provided with an stx and an srx pair. pins txd0{x} and rxd0{x}, where x is the number of the specific phy, are used to perform the stx and srx functions on the BCM5238. the chip has a single sclk and sync input which is common to all phys. pins ref_clk and ssync are used for these functions on the BCM5238. receive data and control information are passed from the phy to the mac in ten-bit frames. in 100 mbps mode, each frame represents a new byte of data. in 10 mbps mode, each byte of data is repeated ten times; the mac can sample any one of every ten frames. since the timing of data coming from a remote transmitter is not synchronized with the local sclk or sync lines and may contain errors in frequency, a fifo capable of storing 28 bits is provided in each receive path. the received data bits and the rx_dv signal are passed through the fifo; the crs bit is not. it is asserted for the time the wire is receiving a frame. if the remote transmitter is idle and no data needs to be passed from the receiver, status information becomes available. transmit data and control information are passed from the mac to the phy in ten-bit frames, as in the receive path. in 100 megabit mode, each frame represents a new byte of data. in 10 mbps mode, each byte of data is repeated ten times; the phy can transmit any one of every ten frames. s ource s ynchronous smii (sssmii) i nterface from a data signaling standpoint, the source synchronous smii is essentially identical to standard smii. the only difference is that source synchronous employs specific 125 mhz clocks and sync signals that travel in the same direction as the data, txd0 and rxd0, and are synchronous to the data. therefore, a source synchronous capable mac which sends txd0 to the phy must also send a source synchronous 125- mhz clock and sync signal to the phy. the phy uses this cloc k and sync to latch-in and delineate the txd0 data stream. similarly, the BCM5238 in source synchronous smii mode drives rxd0 to the mac along with a 125 mhz clock and sync signals. the mac should use this clock and sync to latch-in and delineate rxd0 data streams. by using these separate clock and sync signals, smii timing constraints are significantly eased.
BCM5238 advance data sheet 1/31/03 broadcom corporation page 6 source synchronous smii (sssmii) interface document 5238-ds03-405-r i nterrupt mode the BCM5238 can be programmed to provide an interrupt output consisting of an or of the eight interrupts, one from each phy. the interrupt feature is disabled by default. the interrupt capability is enabled by setting mii register 1ah, bit 14. the status of each interrupt source is also reflected in register 1ah, bits 1, 2 and 3. the sources of interrupt are change in link , speed or full-duplex status. if any type of interrupt occurs, the interrupt status bit, register 1ah, bit 0 is set. in addition, each transceiver has its own register controlling the interrupt function. if the interrupt enable bit is set to 0, no status bits sets and no interrupts are generated. if the interrupt enable bit is se t to 1, the following conditions apply: if mask status bits are set to 0 and the interrupt mask is set to 1, status bits are set, but no interrupts are generated. if mask status bits are set to 0 and the interrupt mask is set to 0, status bits and interrupts are available. if mask status bits are set to 1 and the interrupt mask is set to 0, no status bits and no interrupts are available. changes from active to inactive, or vice versa, cause an interrupt. setting register 1ah, bit 8 high masks all interrupts, regardless of the settings of the individual mask bits.
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r hardware signal definition table page 7 section 2: hardware signal definition table note i = digital input, o = digital output, i/o = bidirectional, i a = analog input, o a = analog output, i pu = digital input with internal pull-up, i pd = digital input with internal pull-down, o od = open-drain output, o 3s = three-state output, i/o pd = bidirectional with internal pull-down, i/o pu = bidirectional with internal pull- up, b = bias voltage table 2: pin definitions BCM5238b BCM5238u pin label i/o description media connections a12,b12 a11,b11 a08,b08 a07,b07 t06,r06 t07,r07 t10,r10 t11,r11 4, 3 6, 7 13, 12 16, 17 23, 22 26, 27 33, 32 35, 36 rd+{1}, rd-{1} rd+{2}, rd-{2} rd+{3}, rd-{3} rd+{4}, rd-{4} rd+{5}, rd-{5} rd+{6}, rd-{6} rd+{7}, rd-{7} rd+{8}, rd-{8} i a receive pair. differential data from the media is received on the rd signal pair. a13,b13 a10,b10 a09,b09 a06,b06 t05,r05 t08,r08 t09,r09 t12,r12 1, 2 9, 8 10,11 19, 18 20, 21 29, 28 30, 31 38, 37 td+{1}, td-{1} td+{2}, td-{2} td+{3}, td-{3} td+{4}, td-{4} td+{5}, td-{5} td+{6}, td-{6} td+{7}, td-{7} td+{8}, td-{8} o a transmit pair. differential data is transmitted to the media on the td signal pair. e16 f16 g16 h16 j16 k16 l16 m16 99 96 94 92 86 84 82 79 txd0{1} txd0{2} txd0{3} txd0{4} txd0{5} txd0{6} txd0{7} txd0{8} i pd transmit data input. serial transmit data from mac to phy d15 e15 f13 g14 h13 j14 k13 l14 100 97 95 93 87 85 83 80 rxd0{1} rxd0{2} rxd0{3} rxd0{4} rxd0{5} rxd0{6} rxd0{7} rxd0{8} o 3s receive data outputs. serial receive data from phy to mac
BCM5238 advance data sheet 1/31/03 broadcom corporation page 8 hardware signal definition table document 5238-ds03-405-r clock signal t15 42 ref_clk i reference clock input. this pin must be driven with a continuous 125-mhz clock. it provides timing for rxd0, txd0, and their associated clocks and sync signals. accuracy shall be 50 ppm, with a duty cycle between 35% and 65% inclusive. phy control and mode signals c16 102 reset i pu reset. active low. resets the BCM5238. pin not included in nand chain. n15 127 f100 i pu 10/100 mode select. when high and anen is low, all transceivers are forced to 100base-x operation. when low and anen is low, all transceivers are forced to 10base-t operation. when anen is high, f100 has no effect on the operation. m13 126 anen i pu auto-negotiation enable. active high. when pulled high, auto-negotiation begins immediately after reset. when low, auto-negotiation is disabled after reset. auto-negotiation can be enabled under software control (register 0, bit 12) if auto-negotiation is enabled through hardware. c15 101 fdxen i pd full-duplex mode enable. the fdxen pin is logically ored with an mii control bit to generate an internal full- duplex enable signal. when fdxen is high, the BCM5238 may operate in full-duplex mode as determined by auto- negotiation. when fdxen is low, the internal control bit (register 0, bit 8) determines the full-duplex operating mode. initial value of the internal control bit is zero. f05 74 mdix_dis i pd hp auto-mdix disable. active high. when pulled high during reset, automatic tx cable swap detection function of the BCM5238 is disabled. leave this pin unconnected for normal operation. f04 117 testen i pd test enable. active high test control input used along with phyad[4:0] to select the nand-chain test mode. this test mode is latched when testen is pulsed high, then low, with phyad[4:0] = 10111. this pin is not included in the nand chain and must be pulled low or left unconnected during normal operation. k02 71 intr / sled_do o od phy interrupt. active low output. this pin becomes interrupt output if ser_en pin is low during power-on reset. sled_do. serial led data. active low serial led data. pin-71 becomes serial led data output if serial_en pin is high during power-on reset. see ?led display output modes? on page 18 for details. table 2: pin definitions (cont.) BCM5238b BCM5238u pin label i/o description
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r hardware signal definition table page 9 h01 65 sssmii_dis/ sled_clk i/o pu sssmii disable. active high. when this pin is high or left unconnected during power-on reset, the BCM5238 enables the serial media independent interface mode (smii). when this pin is low (pull-down) during power-on reset, the smii source synchronous smii mode is enabled. when the smii source synchronous mode is enabled, the BCM5238 provides a source synchronous receive clock (sssmii_rxc) and a sync (sssmii_rsync) for mac to use for receiving data from the phy and the BCM5238 uses smii_txc along with ssync to receive data from the mac. sled_clk. serial led clock. after power-on reset, if serial or low cost serial led mode is enabled, this pin sources the clock for serial data sled_do. see ?led display output modes? on page 18 for details. e10 104 mode_5228 i pu bcm5228 mode select. active high. during power-on if this pin is left unconnected (or pull-up), the BCM5238 mii registers values default to the bcm5228 mii register default values. otherwise, it defaults to the BCM5238 default register values. m08 led1to3 i pll led1 to led3 option. active low. when this pin is low, the bcm5228 led3 will be available on led1. refer to the bcm5228 data sheet for hardware default and mii register programming. note that this option is available only in the BCM5238b. smii and ssmii signals p15 67 ssync i pd sync. in smii mode, this pin must be connected to a free running sync pulse occurring 1 of every 10 clock cycles. data and controls are transferred through txd and rxd between respective mac and phy in default smii mode. if source synchronous enable, sssmii_dis, is low, then ssync provides sync for txd only and sssmii_rsync from the BCM5238 provides sync for rxd. r16 69 sssmii_rxc o 3s smii source synchronous receive clock. optional 125- mhz clock in smii mode for mac use to clock in rxd. p16 70 sssmii_rsync o 3s smii source synchronous sync. in smii mode, this pin provides a source synchronous sync pulse for mac to use for rxd if source synchronous is enabled. t16 66 ssasmii_txc i pd smii source synchronous transmit clock. 125-mhz clock in sssmii mode for BCM5238 to clock in txd if source synchronous mode is enabled. mii register access signals j01 118 mdio i/o pu management data i/o. this serial input/output bit is used to read from and write to the mii registers. the data value on the mdio pin is valid and latched on the rising edge of mdc. k01 119 mdc i pd management data clock. the mdc clock input must be provided to allow mii management functions. clock frequencies up to 25 mhz are supported. g05, h05, h04, j05, j03 47, 48, 49, 50, 51 phyad {4:0} i pd phy address selects. these inputs set the base address for mii management phy addresses. also serve as test control inputs along with testen to select the nand- chain test mode. table 2: pin definitions (cont.) BCM5238b BCM5238u pin label i/o description
BCM5238 advance data sheet 1/31/03 broadcom corporation page 10 hardware signal definition table document 5238-ds03-405-r h02 75 masterphy/ sframe i/o pd master phy address mode. active high. this forces phy address 0 to be a global write address for all phys within the BCM5238. an active high during power-on reset selects the master phy address mode, while an active low or being left unconnected selects the normal address mode. sframe. serial led frame. after power-on reset, this pin sources the serial led frame output signal if serial led mode is enabled. leds and led control signals g03 76 serial_en i pd serial led enable. active high. serial led mode is enabled if this pin is high and lc-ser_en pin is low during power-on reset. serial led mode and low cost serial led mode can not be active at the same time. see ?led display output modes? on page 18 for details. g02 77 lc_ser_en i pu low cost serial led enable. active high. low cost serial led mode is enabled if this pin is high and serial_en pin is high during power-on reset. low cost serial led mode and serial led mode cannot be active at the same time. see ?led display output modes? on page 18 for details. f01, f02, e01, e02, p01, p02, n02, n01 110, 111, 113, 114, 59, 60, 62, 63 led1{1:8} i/o pd led1[1:8]. active low output. this is one of two available parallel led output signals. these pins are sampled during power-on reset to set the default led output for led1 and led2. see ?led display output modes? on page 18 for details. c04, e06, d05, c05, m07, n07, m06, n06 105, 106, 108, 109, 53, 54, 57, 58 led2{1:8} o od led2. active low output. this is one of two available parallel led output signals. see ?led display output modes? on page 18 for details. jtag signals l02 121 tdi i pu test data input. single data input to the jtag tap controller used to traverse the test-logic state machine. sampled on the rising edge of tck. if unused, may be left unconnected. l03 123 tms i pu test mode select. serial control input to the jtag tap controller. sampled on the rising edge of tck. if unused, can be left unconnected. l05 122 tck i pu test clock. clock input used to synchronize the jtag tap control and data transfers. if unused, can be left unconnected. k04 125 tdo o 3s test data output. serial data output from the jtag tap controller. updated on the falling edge of tck. actively driven both high and low when enabled; high impedance otherwise. k05 124 trst i pu test reset. asynchronous active-low reset input to the jtag tap controller. must be held low during power-up to insure the tap controller initializes to the test-logic-reset state; must be pulled low continuously when jtag functions are not used. power, bias, and reference signals a15 45 rdac b dac bias resistor. adjusts the current level of each of the transmit dacs. a resistor of 1.24 k ? 1% must be connected between the rdac pin and agnd. table 2: pin definitions (cont.) BCM5238b BCM5238u pin label i/o description
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r hardware signal definition table page 11 t14 41 pllvdd18 pwr phase locked loop core vdd , 1.8v note: in the bcm5228 core vdd is 2.5v p14 43 pllvddp pwr phase locked loop pad vdd , same supply as ovdd r14 40 pllgnd gnd phase locked loop gnd a16 46 biasvdd33 b bias vdd, same supply as ovdd b16 44 biasgnd gnd bias gnd a05, c07, c10, c13, p07, p11, t04, t13 5, 15, 24, 34 avdd18 pwr analog vdd , 1.8v note: in the bcm5228, analog vdd is 2.5v b05, b14, b15, c06, c08, c09, c11, c12, d09, d10, e09, p05, p06, p08, p09, p10, p12, p13, r04, r13 14, 25, 39, 128 agnd gnd analog gnd e04, e13, g04, k14, l04, n13 56, 73, 90, 116 dvdd18 pwr 1.8v, digital core vdd note that digital core vdd in the bcm5228 is 2.5v c14, f03, g06, j13, m03, n14 52, 64, 78, 89, 91, 103, 115 dgnd gnd digital core and output buffer gnd d06, e03, f14, g13, h03, k03, l13, m14, n08 55, 61, 68, 81, 88, 98, 107, 112, 120 ovdd pwr 3.3v, digital periphery (output buffer) vdd d13, f06, f07, h11, h14, j04, l06, l07, n16 ?ognd gnd digital periphery (output buffer) ground j2 72 internal1 nc factory test (dp) pin . must be left unconnected for normal operation. table 2: pin definitions (cont.) BCM5238b BCM5238u pin label i/o description
BCM5238 advance data sheet 1/31/03 broadcom corporation page 12 hardware signal definition table document 5238-ds03-405-r a01, a02, a03, a04, a14, b01, b02, b03, b04, c01, c02, c03, d01, d02, d03, d04, d07, d08, d11, d12, d14, d16, e05, e07, e08, e11, e12, e14, f12, f15, g01, g12, g15, h12, h15, j12, j15, k12, k15, l01, l12, l15, m01, m02, m04, m05, m09, m10, m11, m12, m15, n03, n04, n05, n09, n10, n11, n12, p03, p04, r01, r02, r03, r15, t01, t02, t03 ?nc ? no connec t. do not connect anything to these pins and do not connect these pins together. f08, f09, f10, f11, g07, g08, g09, g10, g11, h06, h07, h08, h09, h10, j06, j07, j08, j09, j10, j11, k06, k07, k08, k09, k10, k11, l08, l09, l10, l11 ?tgnd ? thermal ground . connect these pins to the ground plane. table 2: pin definitions (cont.) BCM5238b BCM5238u pin label i/o description
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r pinout diagram page 13 section 3: pinout diagram figure 2 is the pinout diagram for the BCM5238u. figure 2: BCM5238u pin diagram ovdd ovdd led1{2} trst# tck tms tdi gnd mode_522 8 led1{3} led1{4} testen dvdd18 mdio mdc gnd led2{2} led2{1} ovdd led2{3} led1{1} led2{4} tdo anen f100 agnd 127 128 125 126 123 124 121 122 119 120 117 118 115 116 113 114 111 112 109 110 107 108 105 106 103 104 BCM5238u 101 102 99 100 97 98 95 96 93 94 91 92 89 90 87 88 85 86 83 84 81 82 79 80 77 78 75 76 73 74 71 72 69 70 67 68 65 66 ovdd txd0{7} rxd0{7} txd0{6} ssync sssmii_rxc ovdd rxd0{8} gnd rxd0{3} rxd0{6} txd0{5} gnd rxd0{1} txd0{1} serial_en mdix_dis master_phy/sframe sssmii_txc sssmii_dis/sled_clk dvdd18 internal1 fdxen reset# sssmii_rsync intr#/sled_do lc_ser_en txd0{8} rxd0{5} ovdd dvdd18 gnd txd0{4} rxd0{4} txd0{3} txd0{2} rxd0{2} ovdd ref_clk pllvddp rdac biasvdd33 phyad2 phyad4 phyad0 dvdd18 led1{8} led1{7} led1{6} biasgnd pllvdd18 42 41 44 43 46 45 48 47 50 49 52 51 54 53 56 55 58 57 60 59 62 61 64 63 phyad3 phyad1 led2{5} led2{6} ovdd led2{7} led2{8} led1{5} ovdd gnd 40 39 pllgnd agnd gnd 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 rd-{8} td+{7} td-{7}} rd+{3} rd-{2} agnd td+{6} td-{5} td+{5} agnd rd-{6} td-{4} rd-{4} td+{1} td-{1} rd-{1} rd+{1} rd-{3} td-{3} rd-{7} td-{6} rd+{8} avdd18 rd+{7} rd+{6} rd-{5} td+{4} rd+{4} avdd18 td+{3} td+{2} td-{2} rd+{2} avdd18 avdd18 rd+{5} td-{8} td+{8}
BCM5238 advance data sheet 1/31/03 broadcom corporation page 14 pinout diagram document 5238-ds03-405-r the pinout diagram for the BCM5238b 256-pin fbga package is shown in figure 3 . figure 3: BCM5238b pin diagram 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 a nc nc nc nc avdd18 td+{4} rd+{4} rd+{3} td+{3} td+{2} rd+{2} rd+{1} td+{1} nc rdac biasvdd3 3 a b nc nc nc nc agnd td-{4} rd-{4} rd-{3} td-{3} td-{2} rd-{2} rd-{1} td-{1} agnd agnd biasgnd b c nc nc nc led2{1} led2{4} agnd avdd18 agnd agnd avdd18 agnd agnd avdd18 dgnd fdxen reset# c d nc nc nc nc led2{3} ovdd nc nc agnd agnd nc nc ognd nc rxd0{1} nc d e led1{3} led1{4} ovdd dvdd18 nc led2{2} nc nc agnd mode_ 5228 nc nc dvdd18 nc rxd0{2} txd0{1} e f led1{1} led1{2} dgnd testen mdix_ dis ognd ognd tgnd tgnd tgnd tgnd nc rxd0{3} ovdd nc txd0{2} f g nc lc_ser_ en serial_ en dvdd18 phyad4 dgnd tgnd tgnd tgnd tgnd tgnd nc ovdd rxd0{4} nc txd0{3} g h sssmii_ dis/ sled_clk masterp hy/ sframe ovdd phyad2 phyad3 tgnd tgnd tgnd tgnd tgnd ognd nc rxd0{5} ognd nc txd0{4} h j mdio internal1 phyad0 ognd phyad1 tgnd tgnd tgnd tgnd tgnd tgnd nc dgnd rxd0{6} nc txd0{5} j k mdc sled_ do/ intr# ovdd tdo trst# tgnd tgnd tgnd tgnd tgnd tgnd nc rxd0{7} dvdd18 nc txd0{6} k l nc tdi tms dvdd18 tck ognd ognd tgnd tgnd tgnd tgnd nc ovdd rxd0{8} nc txd0{7} l m nc nc dgnd nc nc led2{7} led2{5} led1to3 nc nc nc nc anen ovdd nc txd0{8} m n led1{8} led1{7} nc nc nc led2{8} led2{6} ovdd nc nc nc nc dvdd18 dgnd f100 ognd n p led1{5} led1{6} nc nc agnd agnd avdd18 agnd agnd agnd avdd18 agnd agnd pllvddp ssync sssmii_ rsync p r nc nc nc agnd td-{5} rd-{5} rd-{6} td-{6} td-{7} rd-{7} rd-{8} td-{8} agnd pllgnd nc sssmii_ rxc r t nc nc nc avdd18 td+{5} rd+{5} rd+{6} td+{6} td+{7} rd+{7} rd+{8} td+{8} avdd18 pllvdd18 ref_clk sssmii_ txc t 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 note: tgnd balls are thermal grounds
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r operational description page 15 section 4: operational description r esetting the BCM5238 there are two ways to reset each transceiver in the BCM5238. a hardware reset pin has been provided which resets all internal nodes inside the chip to a known state. the reset pulse must be asserted for at least 2 s. hardware reset should always be applied to a BCM5238 after power-up. each transceiver in the BCM5238 also has an individual software reset capability. to perform software reset, a 1 must be written to bit 15 of the transceiver?s mii control register (see ?mii control register? on page 29 ). this bit is self-clearing, meaning that a second write operation is not necessary to end the reset. there is no effect if a 0 is written to the mii contro l register reset bit. phy a ddress each transceiver in the BCM5238 has a unique phy address for mii management. the phy address is determined by the using the base address, which is input on the phyad[4:0] pins. the following shows the addressing of the eight phys. phy0 = phyad + 0, phy1 = phyad + 1,... phy7 = phyad + 7 every time an mii write or read operation is executed, the transceiver compares the phy address with its own phy address definition. the operation is executed only when the addresses match. l oopback m ode the loopback mode allows in-circuit testing of the BCM5238 chip. all packets sent in through the txd pins are looped-back internally to the rxd pins, and are not sent out to the cable. incoming packets on the cable are ignored. the loopback mode may be entered by writing a 1 to bit 14 of the mii control register or by writing a 1 to bit 8 and bit 7 of shadow register 1dh. to resume normal operation, the bits must be 0. f ull - duplex m ode the BCM5238 supports full-duplex operation. while in full- duplex mode, a transceiver can simultaneously transmit and receive packets on the cable. by default, each transceiver in the BCM5238 powers up in half-duplex mode. when auto-negotiation is disabled, full-duplex operation can be enabled either by a pin (fdxen) or by an mii register bit (register 0, bit 8).
BCM5238 advance data sheet 1/31/03 broadcom corporation page 16 10base-t mode document 5238-ds03-405-r when auto-negotiation is enabled, full-duplex capability is advertised by default but can be overridden by a write to the auto- negotiation advertisement register (04h). 10base-t m ode the same magnetics module is used to interface the twisted-pair cable in 10base-t mode and in 100base-tx mode. the data is two-level manchester coded instead of three-level mlt3, and no scrambling/descrambling or 4b5b coding is performed. i solate m ode each transceiver in the BCM5238 can be isolated from the rmi i/smii/s3mii interface. when a transceiver is put into isolate mode, all rmii/smii/s3mii input pins (txd0, ssyncs, smii_txc) are ignored and all smii/s3mii output pins (rxd0, ssmii_rsync, ssmii_rxc) are set at high impedance. mii management pins (mdc, mdio,) and analog td, rd pins operate normally. writing a 1 to bit 10 of the mii control regist er 0 puts the port into isolate mode. writing a 0 to the same bit removes it from isolate mode. upon resetting the chip or resetting the isolated port, the isolate mode is off. s uper i solate m ode when the chip is in super isolate mode, in addition to isolate mode actions, the chip also sets the analog td pins to high impedance. writing a 1 to bit 3 of the mii register 1eh puts t he port into super isolate mode. writing a 0 to the same bit removes it from super isolate mode. upon resetting the chip or resetting the isolated port, the super isolate mode is off. a uto p ower -d own m ode the BCM5238 supports a low power mode called auto power-down mode. auto power-down mode is enabled by setting bit 5 of shadow register 1bh. when in this mode, the BCM5238 automatically enters the low power mode if the energy from the link partner is lost. similarly, the next time energy is detected, the chip resumes full power mode. when the BCM5238 is in this low power mode, it wakes up after approximately 2.5 to 5.0 seconds, as determined by bit 4 of shadow register 1bh, and sends a link pulse while monitoring energy from the link partner. if energy is detected, the BCM5238 enters full power mode and establishes link with the link partner. otherwise, the wake-up mode continues for a duration of approximately 40? 600 ms, as determined by bits [3:0] of shadow register 1bh before going to low power mode. see table47onpage53 for details of various bits. j umbo p acket m ode in 100base-x mode, the BCM5238 can support jumbo packet sizes. the size of the packet that can be handled reliably depends on the descrambler lock timer settings and the receive fifo size. by default, the BCM5238 provides an effective 10 bits receive fifo to accommodate the minor clock deviations of the link partner. additionally , the BCM5238 incorporates
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r jumbo packet mode page 17 extended fifo modes to allow for extremely large packet sizes. these modes are enabled by setting appropriate bits in the mii registers. the following table shows the number of effective fifo bits supported. when changing the receive fifo size, it is necessary to identify the receive packet size requirement and set the descrambler timer lock accordingly. the descrambler timer lock is controlled by jumbo packet enable bit located in register 1bh, bit 10. the following table shows the descrambler lock timer allowed by this bit and the corresponding packet size. note that the packet size that can be reliably received is the lower number indicated by two settings: jumbo packet enable bit two extended fifo enable bits table 3: receive fifo size select jumbo packet fifo enable reg 1bh bit 9 extended fifo enable reg 10h bit 2 number of effective fifo bits supported packet size in bytes b b. packet size calculation?based on 50 ppm clock tolerance for local and link partner. 0 0 10 12,500 0 1 20 25,000 1 0 20 25,000 11 40 (20) a a. in this mode, the BCM5238 operation is guaranteed to only to 20 bits effective fifo depth, although under some circumstances, it could behave as if the fifo depth is 40 bits. 50,000/25,000 table 4: jumbo packet enable and descrambler lock timer jumbo packet enable reg 1bh bit 10 descrambler lock timer packet size 0 724 s 9050 1 5792 s 72400
BCM5238 advance data sheet 1/31/03 broadcom corporation page 18 led display output modes document 5238-ds03-405-r section 5: led display output modes d escription the BCM5238 offers a rich set of led display outputs through serial, parallel, and extended parallel led modes. there are two serial led modes available, serial led mode and low-co st serial led mode. serial led modes are selected by hardware only during power-on reset. s erial led m ode serial led mode is enabled only by holding the serial_en pin high and lc_ser_en pin low during power-on reset. if serial led mode is enabled, low-cost serial led mode is disabled. in serial led mode the BCM5238 sources a serial data stream, the associated clock, and a framing signal as follows: a serial data stream, sled_do, which is an active low bit stream containing 48 bits per frame. a serial data clock, sled_clk, which runs at approximately 2 mhz to clock out sled_do on the falling edge of this clock. sled_do is valid on the rising edge of this clock. a framing pulse, sframe, which is an active high pulse occurring once every 48 sled_do bit times. sframe goes high coincident with bit 0 of port 1. the BCM5238 provides two different serial led streams, described below: when the serial led mode is enabled by hardware, and no further action is taken, the led stream is selected for sled_do (as shown in ta bl e 5 ) depending on the values of bit 14 and 15 of mii register 1ah. the data stream contains bit 0 to bit 5 for port 1, bit 0 to bit 5 for port 2, ..., bit 0 to bit 5 for port 8. note?a global interrupt indicates an interrupt from any of the eight phy as if they were ored together. a port interrupt is provided on a per phy basis. if mii shadow register 1ah (of phy 2 of 8) bit 9, serial led program enable, is set to a 1, then the serial led stream is selected by the serial bank select bits as specified in ta bl e 6 , ta bl e 7 , ta b l e 8 , ta bl e 9 , ta b l e 1 0 and ta bl e 1 1 . led stream will contain bank 1 output for port 1 through port 8, bank 2 output for port 1 through port 8, ..., bank 6 output for port 1 through port 8. table 5: serial led mode bit framing register 1ah serial bit 5 serial bit 4 serial bit 3 serial bit 2 serial bit 1 serial bit 0 bit 15 = 0 bit 14 = 0 fdx col speed100 link transmit receive bit 15 = 0 bit 14 = 1 fdx global interrupt speed100 link port interrupt activity bit 15 = 1 bit 14 = 0 fdx col speed100 link fdx activity bit 15 = 1 bit 14 = 1 fdx global interrupt speed100 link fdx activity
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r serial led mode page 19 l ow - cost s erial led m ode the low-cost serial led mode is enabled by pulling both lc_ser_en pin and ser_en pin high during power-on reset. when enabled, the serial led data stream, sled_do, is shifted out on the falling edge of sled_clk. sled_do is valid on the rising edge of this clock. the data is shifted so that the update of leds using a shift register to drive the display l eds does not cause noticeable flicker in normal operation. there are six banks, bank 1 through bank 6, associated with six led outputs. each bank has its own mii register bits that select a led signal to output from that bank. selected signal from each bank is shifted out on the led_do pin in the following order: bank 1 for port 1 through port 8, bank 2 for port 1 through port 8,...., and bank 6 for port 1 through 8 for a total of 48 led outputs. the low cost serial led mode programmable banks are located in the mii shadow register 1ah of phy 2, 3 and 4. see table 6 , table 7 , table 8 , table 9 , table 10 and table 11 for programming details. the default led outputs are speed, link, full-duplex, activity, speed, and link for bank 1 through bank 6, respectively. table 6: serial mode bank 1 led selection mii shadow register 1ah, (phy 4 of 8), bits [2:0] value led selection serial bank 1 select bits [2:0] 0 speed 1 activity 2 full-duplex 3transmit 4 receive 5 interrupt 6 collision 7link note: mii shadow register is accessed by setting mii register 1fh bit 7 to a 1. table 7: serial mode bank 2 led selection mii shadow register 1ah, (phy 4 of 8), bits [5:3] value led selection serial led bank 2 select bits [2:0] 0 link 1 speed 2 activity 3 full-duplex 4transmit 5 receive 6 interrupt 7 collision note: mii shadow register is accessed by setting mii register 1fh bit 7 to a 1.
BCM5238 advance data sheet 1/31/03 broadcom corporation page 20 serial led mode document 5238-ds03-405-r table 8: serial mode bank 3 led selection mii shadow register 1ah, (phy 3 of 8), bits [2:0] value led selection serial led bank 3 select bits [2:0] 0 full-duplex 1transmit 2 receive 3 interrupt 4 collision 5link 6 speed 7 activity note: mii shadow register is accessed by setting mii register 1fh bit 7 to a 1. table 9: serial mode bank 4 led selection mii shadow register 1ah, (phy 4 of 8), bits [5:3] value led selection serial led bank 4 select bits [2:0] 0 activity 1 full-duplex 2 transmit 3 receive 4 interrupt 5 collision 6link 7 speed note: mii shadow register is accessed by setting mii register 1fh bit 7 to a 1.
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r serial led mode page 21 table 10: serial mode bank 5 led selection mii shadow register 1ah, (phy 2 of 8), bits [2:0] value led selection serial led bank 5 select bits [2:0] 0 speed 1activity 2 full-duplex 3transmit 4 receive 5 interrupt 6 collision 7link note: mii shadow register is accessed by setting mii register 1fh bit 7 to a 1. table 11: serial mode bank 6 led selection mii shadow register 1ah, (phy 2 of 8), bits [5:3] value led selection serial bank 6 select bits [2:0] 0 link 1 speed 2 activity 3 full-duplex 4transmit 5 receive 6 interrupt 7 collision note: mii shadow register is accessed by setting mii register 1fh bit 7 to a 1.
BCM5238 advance data sheet 1/31/03 broadcom corporation page 22 serial led mode document 5238-ds03-405-r p arallel led m ode there are two led pins, led1 and led2, for each port. each can be individually configured to output one of many phy status or forced signals. these two leds are referred to as parallel leds and they are always enabled. for unmanaged system design using the BCM5238, the parallel led pins for each port can be programmed through hardware during power- on reset by pull-down or pull-up combinations of led1{1:6} pins. see table 12 and table 13 for details. software configuration of led1 and led2 is accomplished throug h mii shadow register 1ah, phy 1, bits [5:0] if parallel led select enable, bit 9, of mii shadow register 1ah, phy 1 is set to a 1. the shadow register is enabled by setting bit 7 of mii register 1fh. see table 12 and table 13 for details. note that in this mode, after the programming specified in table 12 and table 13 (either through power-on reset or through software), led1 and led2 outputs provide the same status outputs for all eight ports. table 12: parallel led mode led1 selection led1{3:1} mii shadow register 1ah, phy 1, bits [2:0] value led1 selection power-on led1 select bits [2:0] led1 select [2:0] 0 link 1 speed 2 activity 3 full-duplex 4transmit 5receive 6 interrupt 7 collision note: mii shadow register is accessed by setting mii register 1fh bit 7 to a 1. table 13: parallel led mode led2 selection led1{6:4} mii shadow register 1ah, phy 1, bits [5:3] value led2 selection power-on led2 select bits [2:0] led2 select [2:0] 0 speed 1activity 2 full-duplex 3 transmit 4 receive 5 interrupt 6 collision 7link note: mii shadow register is accessed by setting mii register 1fh bit 7 to a 1.
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r transmit and receive led behavior page 23 e xtended p arallel led m ode in parallel led mode, the BCM5238 can be programmed to output different status signals, other than what is specified in table 12 and table 13 , on led1 and led2 for each port by enabling extended led mode. extended led mode is enabled, only by software, by setting bit 9 of mii shadow register 1ah of phy 3 (3 of 8) to a 1. when this mode is selected, led1 and led2 for each port can be individually specified to the output status as specified in table 14 below. t ransmit and r eceive led b ehavior normally, whenever an led is set to output the transmit status or receive status of a phy, the led blinks whenever there is transmit or receive activity in that phy. the led can output a different status, however, depending on certain bits in the mii register. t ransmit led when an led is set to output the transmit status of a phy, the led can output the interrupt status of the phy if the interrupt enable bit 14 of mii register 1ah for that phy is set to 1. r eceive led when an led is set to output the receive status of a phy, it becomes a blinking link status of that phy if activity/link led enable bit 2 of mii register 1bh is set to 1. a blinking link led is an led that is on if the link is active and blinks whenever there is transmit or receive activity. table 14: extended parallel led selection extended led1 select[2:0] shadow register 1ah extended led2 select[2:0] shadow register 1ah select[2:0] value led output phy 1: 1ah (of phy 1) bits[2:0] phy 2: 1ah (of phy 2) bits[2:0] phy 3: 1ah (of phy 3) bits[2:0] phy 4: 1ah (of phy 4) bits[2:0] phy 5: 1ah (of phy 5) bits[2:0] phy 6: 1ah (of phy 6) bits[2:0] phy 7: 1ah (of phy 7) bits[2:0] phy 8: 1ah (of phy 8) bits[2:0] phy 1: 1ah (of phy 1) bits[5:3] phy 2: 1ah (of phy 2) bits[5:3] phy 3: 1ah (of phy 3) bits[5:3] phy 4: 1ah (of phy 4) bits[5:3] phy 5: 1ah (of phy 5) bits[5:3] phy 6: 1ah (of phy 6) bits[5:3] phy 7: 1ah (of phy 7) bits[5:3] phy 8: 1ah (of phy 8) bits[5:3] 0link 1 speed 2transmit 3 receive 4off 5on 6 blink: led is on for 160 ms and off for 160 ms. note that if both leds are set to select this option, then led1 will be out of phase with led2. 7 blink: led is on for 40 ms and off for 40 ms. note that if both leds are set to select this option, then led1 will be out of phase with led2.
BCM5238 advance data sheet 1/31/03 broadcom corporation page 24 register summary document 5238-ds03-405-r section 6: register summary mii m anagement i nterface : r egister p rogramming the bcm5248 fully complies with the ieee 802.3u media independent interface (mii) specification. the mii management interface registers of each port are serially written-to and read-from using a common set of mdio and mdc pins. a single clock waveform must be provided to the bcm5248 at a rate of 0?25 mhz through the mdc pin. the serial data is communicated on the mdio pin. every mdio bit must have the same period as the mdc clock. the mdio bits are latched on the rising edge of the mdc clock. every mii read or write instruction frame contains the following fields: preamble (pre). thirty-two consecutive 1 bits must be sent through the mdio pin to the bcm5248 to signal the beginning of an mii instruction. fewer than 32 1 bits causes the remainder of the instruction to be ignored. start of frame (st). a 01 pattern indicates that the start of the instruction follows. opcode (op). a read instruction is indicated by 10, while a write instruction is indicated by 01. phy address (phyad). a 5-bit phy address follows next, with the msb transmitted first. the phy address allows a single mdio bus to access multiple phy chips. the bcm5248 supports a complete address space with phyad[4:0] input pins used as the base address for selecting one of the eight transceivers. register address (regad). a 5-bit register address follows, with the msb transmitted first. the register maps of the BCM5238, which contains register addresses and bit definitions, are provided in table16onpage26 and table17onpage28 . turnaround (ta). the next two bit times are used to avoid contention on the mdio pin when a read operation is performed. for a write operation, 10 must be sent to the bcm5248 chip during these two bit times. for a read operation, the mdio pin must be placed into high-impedance during these two bit times. the chip drives the mdio pin to 0 during the second bit time. data. the last 16 bits of the frame are the actual data bits. for a write operation, these bits are sent to the BCM5238, whereas, for a read operation, these bits are driven by the BCM5238. in either case, the msb is transmitted first. when writing to the BCM5238, the data field bits must be stable 10 nanoseconds before the rising-edge of mdc, and must be held valid for 10 ns after the rising edge of mdc. when reading from the BCM5238, the data field bits are valid after the rising- edge of mdc until the next rising-edge of mdc. idle. a high-impedance state of the mdio line. all tri-state drivers are disabled and the pull-up resistor of the phy pulls the mdio line to logic 1. note that at least one or more idle states are required between frames. following are two examples of mii write and read instructions. to put a transceiver with phy address 00001 into loopback mode, the following mii write instruction must be issued: 1111 1111 1111 1111 1111 1111 1111 1111 0101 00001 00000 10 0100 0000 0000 0000 1... to determine if a phy is in the link pass state, the following mii read instruction must be issued: table 15: mii management frame format operation pre st op phyad regad ta data idle direction read 1 ... 1 01 10 aaaaa rrrrr zz z0 z...z d ... d z z driven to bcm5248 driven by bcm5248 write 1 ... 1 01 01 aaaaa rrrrr 10 d ... d z driven to bcm5248
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r mii management interface: register programming page 25 1111 1111 1111 1111 1111 1111 1111 1111 0110 00001 00001 zz zzzz zzzz zzzz zzzz 1... for the mii read operation, the bcm5248 drives the mdio line during the ta and data fields (the last 17 bit times). a final 65th clock pulse must be sent to close the transaction and cause a write operation to take place. mii r egister m ap s ummary table16onpage26 and table17onpage28 contains the mii register map summary for each port of the bcm5248 . the register addresses are specified in hex form, and the name of register bits have been abbreviated. when writing to any register, preserve existing values of the reserved bits by completing a read/modify write. ignore reserved bits when reading registers. never write to an undefined register. the reset values of the registers are shown in the init column. some of these values could be different depending on how the device is configured and also depending on the device revision value.
BCM5238 advance data sheet 1/31/03 broadcom corporation page 26 mii management interface: register programming document 5238-ds03-405-r table 16: mii register map summary addr name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 init 00h control soft reset loopback force100 auoneg enable power down isolate restart auoneg full duplex collision test reserved 3000h 01h status t4 capable tx fdx capable tx capable bt fdx capable 10bt capable reserved mf pream suppress auoneg comp remote fault autoneg capable link status jabber detect extd reg capable 7809h 02h phyid high 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0040h 03h phyid low 011000 100 model# 000 revision # 0 0 0 0 6200h 04h autoneg advertis e next page reserved remote fault reserved tech pause adv t4 adv tx fdx adv tx adv bt fdx adv bt advertised selector field [4:0] 0 0 0 0 1 01e1h 05h link partner ability lp next page lp acknowlg lp rem fault reserved tech lp pause lp t4 lp tx fdx lp tx lp bt fdx lp bt link partner selector field [4:0] 0000h 06h autoneg expansio n reserved par det fault lp next pg able next pg able page recvd lp auto neg able 0004h 07h next page next page reserved message page acknowledge2 toggle message/unformatted code field 2001h 08h lp next page next page reserved message page acknowledge2 toggle message/unformatted code field 0000h 10h 100base-x aux control reserved trans disable reserved bypass 4b5b enc/dec bypass scram/ descram bypass nrzi enc/dec bypass rcv sym align baseline wander disable fef enable reserved extended fifo enable reserved 0000h 11h 100base-x aux status reserved smii over/ under run reserved locked current 100 link status current remote fault reserved false carrier detected bad esd detected rcv error detected xmt error detected lock error detected mlt3 error detected 0000h 12h 100base-x rcv error counter receive error counter [15:0] 0000h 13h 100base-x false carrier counter smii overrun/underrun counter [7:0] false carrier sense counter [7:0] 0000h 14h 100base-x disconne ct counter smii fastrxd smii slowrxd reserved disconnect counter[7:0] 0200h 15h reserve d reserved 0300h 16h reserve d reserved 0000h 17h ptest reserved 0000h 18h auxiliary control/ status jabber disable force link reserved txdac power mode hsq lsq edge rate [1:0] autoneg enable indicator force 100 indicator sp100 indicator fdx indicator 003xh 19h auxiliary status summary auto neg complete auto neg complete ack auto neg ack detect autoneg ability detect autoneg pause autoneg hcd autoneg pardet fault lp remote fault lp page rcvd lp autoneg able sp100 indicator link status internal autoneg enabled full duplex indication 0000h 1ah interrup t fdx led enable intr enable reserved fdx mask spd mask link mask intr mask reserved global interrupt status fdx change spd change link change intr status 0f0xh 1bh auxiliary mode2 reserved 10bt dribble correct jumbo packet enable jumbo packet fifo enable reserved block 10bt echo mode traffic meter led mode activity led force on serial led enable (phy 1/8) sqe disable activity/link led enable qual parallel detect mode reserved 008ah
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r mii management interface: register programming page 27 1ch 10base-t aux. error and general status reserved mdix status mdix manual swap hp auto- mdix disable 10bt manchstr code err (bt) eof err (bt) reserved 0 0 1 reserved autoneg enable indicator force 100 indicator sp100 indicator fdx indicator 002xh 1dh auxiliary mode reserved reserved activity led force inactive link led force inactive reserved block txen mode reserved x000h 1eh auxiliary multi-phy hcd tx fdx hc t4 hcd tx hcd 10bt fdx hcd 10bt reserved restart autoneg autoneg complete complete ack ack detect ability detect super isolate reserved 10bt serial mode rxer code mode 0000h 1fh broadco m test reserved shadow register enable reserved 000bh table 16: mii register map summary (cont.) addr name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 init
BCM5238 advance data sheet 1/31/03 broadcom corporation page 28 mii management interface: register programming document 5238-ds03-405-r table 17: mii shadow register map summary (mii register 1fh, bit7 = 1) addr name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 init 18h reserve d reserved 003ah 19h reserve d reserved 0000h 1ah auxiliary mode 4 (phy 1 of 8) reserved parallel mii led select enable reserved parallel led2 / extended led2 (phy 1 of 8) select [2:0] parallel led1 / extended led1 (phy 1 of 8) select [2:0] 3000h 1ah auxiliary mode 4 (phy 2 of 8) reserved serial led program enable reserved serial led bank 6 / extended led2 (phy 2 of 8) select [2:0] serial led bank 5/ extended led1 (phy 2 of 8) select [2:0] 3000h 1ah auxiliary mode 4 (phy 3 of 8) reserved extended led enable reserved serial led bank 4 / extended led2 (phy 3 of 8) select [2:0] serial led bank 3 / extended led1 (phy 3 of 8) select [2:0] 3000h 1ah auxiliary mode 4 (phy 4 of 8) reserved serial led bank 2 / extended led2 (phy 4 of 8) select [2:0] serial led bank 1/ extended led (phy 4 of 8) select [2:0] 3000h 1ah auxiliary mode 4 (phy 5 of 8) reserved extended led2 (phy 5 of 8) select [2:0] extended led1 (phy 5 of 8) select [2:0] 3000h 1ah auxiliary mode 4 (phy 6 of 8) reserved extended led2 (phy 6 of 9) select [2:0] extended led1 (phy 6 of 8) select [2:0] 3000h 1ah auxiliary mode 4 (phy 7 of 8) reserved extended led2 (phy 7 of 8) select [2:0] extended led1 (phy 7 of 8) select [2:0] 3000h 1ah auxiliary mode 4 (phy 8 of 8) reserved extended led2 (phy 8 of 8) select [2:0] extended led1 (phy 8 of 8) select [2:0] 3000h 1bh auxiliary status 2 mlt3 detect cable length 100x [2:0] adc peak amplitude [5:0] apd enable apd sleep timer apd wake-up timer[3:0] 0001h 1ch auxiliary status 3 noise [7:0] (root mean square error) flp detect nlp detect link break timer expire link fail timer expire fifo comsumption[3:0] 0000h 1dh auxiliary mode 3 reserved fifo size select [3:0] 0004h 1eh auxiliary status4 packet length counter [15:0] 0000h
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r mii management interface: register programming page 29 mii c ontrol r egister lsoft reset. to reset the bcm5248 by software control, a 1 must be written to bit 15 of the control register using an mii write operation. the bit clears itself after the reset process is complete, and need not be cleared using a second mii write. writes to other control register bits will have no effect until the reset process is completed, which requires approximately 1 s. writing a 0 to this bit has no effect. since this bit is self-clearing, after a few cycles from a write operation, it return s a 1 when read. loopback. the bcm5248 may be placed into loopback mode by writing a 1 to bit 14 of the control register. the loopback mode may be cleared by writing a 0 to bit 14 of the control register, or by resetting the chip. when this bit is read, it retur ns a 0 when the chip is in software-controlled loopback mode, otherwise it returns a 0. forced speed selection. if auto-negotiation is enabled, this bit has no effect on the speed selection. however, if auto- negotiation is disabled by software control, the operating speed of the bcm5248 can be forced by writing the appropriate value to bit 13 of the control register. writing a 1 to this bit forces 100base-x operation, while writing a 0 forces 10base-t operation. when this bit is read, it returns the value of the software-controlled forced speed selection only. to read the overall state of forced speed selection, including both hardware and software control, use bit 2 of the auxiliary erro r and general status register, 1ch. auto-negotiation enable. auto-negotiation can be disabled either by hardware or software control. if the anen input pin is driven to a logic 0, auto-negotiation is disabled by hardware control. if bit 12 of the control register is written with a v alue of 0, auto-negotiation is disabled by software control. when auto-negotiation is disabled in this manner, writing a 1 to the same bit of the control register or resetting the chip re-enables auto-negotiation. writing to this bit has no effect when auto - negotiation has been disabled by hardware control. when read, this bit returns the value most recently written to this location , or 1 if it has not been written since the last chip reset. power down. the bcm5248 does not have a low power mode. table 18: mii control regi ster (address 00d, 00h) bit name r/w description default 15 soft reset r/w (sc) 1 = phy reset 0 = normal operation 0 14 loopback r/w 1 = loopback mode 0 = normal operation 0 13 forced speed selection r/w 1 = 100 mbps 0 = 10 mbps 1 12 auto-negotiation enable r/w 1 = auto-negotiation enable 0 = auto-negotiation disable 1 11 power down ro 0 = normal operation 0 10 isolate r/w 1 = electrically isolate phy from smii 0 = normal operation 0 9 restart auto-negotiation r/w (sc) 1 = restart auto-negotiation process 0 = normal operation 0 8 duplex mode r/w 1 = full-duplex 0 = half-duplex 0 7:0 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ?? 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
BCM5238 advance data sheet 1/31/03 broadcom corporation page 30 mii status register document 5238-ds03-405-r isolate. each individual phy may be isolated from its media independent interface by writing a 1 to bit 10 of the control register. all rxd0{n} outputs is tri-stated and all txd0{n} inpu ts are ignored. since the mii management interface is still active, the isolate mode may be cleared by writing a 0 to bit 10 of the control register, or by resetting the chip. when this b it is read, it returns a 1 when the chip is in isolate mode, otherwise it returns a 0. restart auto-negotiation. bit 9 of the control register is a self-clearing bit that allows the auto-negotiation process to be restarted, regardless of the current status of the auto-negotiation state machine. in order for this bit to have an effect, aut o- negotiation must be enabled. writing a 1 to this bit restarts the auto-negotiation, while writing a 0 to this bit has no effect . since the bit is self-clearing after only a few cycles, it always returns a 0 when read. the operation of this bit is identical to bit 9 of the auxiliary multiple phy register. duplex mode. by default, the bcm5248 powers up in half-duplex mode. the chip can be forced into full-duplex mode by writing a 1 to bit 8 of the control register while auto-negotiation is disabled. half-duplex mode can be resumed by writing a 0 to bit 8 of the control register, or by resetting the chip. mii s tatus r egister 100base-t4 capability. the bcm5248 is not capable of 100base-t4 operation and returns a 0 when bit 15 of the status register is read. 100base-tx fdx capability. the bcm5248 is capable of 100base-tx full-duplex operation and returns a 1 when bit 14 of the status register is read. table 19: mii status register (address 01d, 01h) bit name r/w description default 15 100base-t4 capability ro 0 = not 100base-t4 capable 0 14 100base-tx fdx capability ro 1 = 100base-tx full-duplex capable 1 13 100base-tx capability ro 1 = 100base-tx half-duplex capable 1 12 10base-t fdx capability ro 1 = 10base-t full-duplex capable 1 11 10base-t capability ro 1 = 10base-t half-duplex capable 1 10:7 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ? ? 0000 6 mf preamble suppression r/w 1 = preamble may be suppressed 0 = preamble always required 0 5 auto-negotiation complete ro 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 0 4 reserved ro ignore when read 0 3 auto-negotiation capability ro 1 = auto-negotiation capable 0 = not auto-negotiation capable 1 2 link status ro ll 1 = link is up (link pass state) 0 = link is down (link fail state) 0 1 jabber detect ro lh 1 = jabber condition detected 0 = no jabber condition detected 0 0 extended capability ro 1 = extended register capable 1 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r phy identifier registers page 31 100base-tx capability. the bcm5248 is capable of 100base-tx half-duplex operation and returns a 1 when bit 13 of the status register is read. 10base-t fdx capability. the bcm5248 is capable of 10base-t full-duplex operation and returns a 1 when bit 12 of the status register is read. 10base-t capability. the bcm5248 is capable of 10base-t half-duplex operation and returns a 1 when bit 11 of the status register is read. mf preamble suppression. this bit is the only writable bit in the status register. setting this bit to a 1 allows subsequent mii management frames to be accepted with or without t he standard preamble pattern. when preamble suppression is enabled, only 2 preamble bits are required between successive management commands, instead of the normal 32. auto-negotiation complete. bit 5 of the status register returns a 1 if the auto-negotiation process has been completed and the contents of registers 4, 5 and 6 are valid. auto-negotiation capability. the bcm5248 is capable of performing ieee auto-negotiation and returns a 1 when bit 4 of the status register is read, regardless of whether or not the auto-negotiation function has been disabled. link status. the bcm5248 returns a 1 on bit 2 of the status register when the link state machine is in link pass, indicating that a valid link has been established. otherwise, it returns 0. when a link failure occurs after the link pass state has been entered, the link status bit is latched at 0 and remains so until the bit is read. after the bit is read, it becomes 1 if the l ink pass state has been entered again. jabber detect. 10base-t operation only. the bcm5248 returns a 1 on bit 1 of the status register if a jabber condition has been detected. after the bit is read, or if the chip is reset, it reverts to 0. extended capability. the bcm5248 supports extended capability registers and returns a 1 when bit 0 of the status register is read. several extended registers have been implemented in the bcm5248 and their bit functions are defined later in this section. phy i dentifier r egisters broadcom corporation has been issued an organizationally unique identifier (oui) by the ieee. it is a 24-bit number (00-10-18) expressed as hexadecimal values. that number, along with the broadcom model number for the BCM5238 part (20h) and broadcom revision number (00h) is placed into tw o mii registers. the translation from oui, model number, and revision number to the phy identifier register occurs as follows: phyid high[15:0] = oui[21:6] phyid low[15:0] = oui[5:0] + model[5:0] + rev[3:0] note that the two most significant bits of the oui are not represented (oui[23:22]). table 20: phy identifier registers (addresses 02d and 03d, 02h and 03h) bit name r/w description value 15:0 mii address 00010 ro phyid high 0040h 15:0 mii address 00011 ro phyid low 6200h
BCM5238 advance data sheet 1/31/03 broadcom corporation page 32 auto-negotiation advertisement register document 5238-ds03-405-r table20onpage31 shows the result of concatenating these values in order to form the mii identifier registers phyid high and phyid low. a uto -n egotiation a dvertisement r egister next page. the bcm5248 supports next page function. remote fault. writing a 1 to bit 13 of the advertisement register causes a remote fault indicator to be sent to the link partner during auto-negotiation. writing a 0 to this bit or resetting the chip clears the remote fault transmission bit. this bit retur ns the value last written to it, or else 0 if no write has been completed since the last chip reset. reserved technologies. ignore output when read. pause. pause operation for full-duplex links. the use of this bit is independent of the negotiated data rate, medium, or link technology. the setting of this bit indicates the availability of additional dte capability when full-duplex operation is in us e. this bit is used by one mac to communicate pause capability to its link partner and has no effect on phy operation. advertisement bits. bits 9:5 of the advertisement register allow the user to customize the ability information transmitted to the link partner. the default value for each bit reflects the abilities of the bcm5248 . by writing a 1 to any of the bits, the corresponding ability is transmitted to the link partner. writing a 0 to any bit causes the corresponding ability to be suppressed from transmission. resetting the chip restores the default bit values. reading the register returns the values last written to the corresponding bits, or else the default values if no write has been completed since the last chip reset. advertise selector field. bits 4:0 of the advertisement register contain the value 00001, indicating that the chip belongs to the 802.3 class of phy transceivers. table 21: auto-negotiation advertisement register (address 04d, 04h) bit name r/w description default 15 next page r/w 1 = next page ability is enabled 0 = next page ability is disabled 0 14 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ?? 0 13 remote fault r/w 1 = transmit remote fault 0 12:11 reserved technologies ro ignore when read 00 10 pause r/w 1 = pause operation for full-duplex 0 9 advertise 100base-t4 r/w 1 = advertise t4 capability 0 = do not advertise t4 capability 0 8 advertise 100base-x fdx r/w 1 = advertise 100base-x full-duplex 0 = do not advertise 100base-x full-duplex 1 7 advertise 100base-x r/w 1 = advertise 100base-x 1 6 advertise 10base-t fdx r/w 1 = advertise 10base-t full-duplex 0 = do not advertise 10base-t full-duplex 1 5 advertise 10base-t r/w 1 = advertise 10base-t 1 4:0 advertise selector field r/w indicates 802.3 00001 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r auto-negotiation advertisement register page 33 a uto -n egotiation l ink p artner (lp) a bility r egister note that the values contained in the auto-negotiation link partner ability register are only guaranteed to be valid once auto-negotiation has successfully completed, as indicated by bit 5 of the mii status register. lp next page. bit 15 of the link partner ability register returns a value of 1 when the link partner implements the next page function and has next page information that it wants to transmit. the bcm5248 does not implement the next page function, and thus ignores the next page bit, except to copy it to this register. lp acknowledge. bit 14 of the link partner ability register is used by auto-negotiation to indicate that a device has successfully received its link partner?s link code word. lp remote fault. bit 13 of the link partner ability register returns a value of 1 when the link partner signals that a remote fault has occurred. the bcm5248 simply copies the value to this register and does not act upon it. reserved bits. ignore when read. lp advertise pause. indicates that the link partner pause bit is set. lp advertise bits. bits 9:5 of the link partner ability register reflect the abilities of the link partner. a 1 on any of these bits indicates that the link partner is capable of performing the corresponding mode of operation. bits 9:5 are cleared any time auto-negotiation is restarted or the BCM5238 is reset. lp selector field. bits 4:0 of the link partner ability register reflect the value of the link partner?s selector field. these bits are cleared any time auto-negotiation is restarted or the chip is reset. table 22: auto-negotiation link partner ability register (address 05d, 05h) bit name r/w description default 15 lp next page ro link partner next page bit 0 14 lp acknowledge ro link partner acknowledge bit 0 13 lp remote fault ro link partner remote fault indicator 0 12:11 reserved technologies ro ignore when read 000 10 lp advertise pause ro link partner has pause capability 0 9 lp advertise 100base-t4 ro link partner has 100base-t4 capability 0 8 lp advertise 100base-x fdx ro link partner has 100base-x fdx capability 0 7 lp advertise 100base-x ro link partner has 100base-x capability 0 6 lp advertise 10base-t fdx ro link partner has 10base-t fdx capability 0 5 lp advertise 10base-t ro link partner has 10base-t capability 0 4:0 link partner selector field ro link partner selector field 00000 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
BCM5238 advance data sheet 1/31/03 broadcom corporation page 34 auto-negotiation advertisement register document 5238-ds03-405-r a uto -n egotiation e xpansion r egister parallel detection fault. bit 4 of the auto-negotiation expansion register is a read-only bit that gets latched high when a parallel detection fault occurs in the auto-negotiation state machine. for further details, consult the ieee standard. the bit is reset to 0 after the register is read, or when the chip is reset. link partner next page able. bit 3 of the auto-negotiation expansion register returns a 1 when the link partner has next page capabilities. it has the same value as bit 15 of the link partner ability register. next page able. the bcm5248 returns 1 when bit 2 of the auto-negotiation expansion register is read indicating that it has next page capabilities. page received. bit 1 of the auto-negotiation expansion register is latched high when a new link code word is received from the link partner, checked, and acknowledged. it remains high until the register is read, or until the chip is reset. link partner auto-negotiation able. bit 0 of the auto-negotiation expansion register returns a 1 when the link partner is known to have auto-negotiation capability. before any auto-negotiation information is exchanged, or if the link partner does not comply with ieee auto-negotiation, the bit returns a value of 0. table 23: auto-negotiation expans ion register (address 06d, 06h bit name r/w description default 15:5 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ? ? 000h 4 parallel detection fault ro lh 1 = parallel detection fault. 0 = no parallel detection fault 0 3 link partner next page able ro 1 = link partner has next page capability 0 = link partner does not have next page capability 0 2 next page able ro 1 = next page able 1 1 page received ro 1 = new page has been received 0 = new page has not been received 0 0 link partner auto-negotiation able ro lh 1 = link partner has auto-negotiation capability 0 = link partner does not have auto-negotiation capability 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r auto-negotiation advertisement register page 35 a uto -n egotiation n ext p age r egister next page. indicates whether this is the last next page to be transmitted. message page. differentiates a message page from an unformatted page. acknowledge 2. indicates that a device has the ability to comply with the message. toggle. used by the arbitration function to ensure synchronization with the link partner during next page exchange. message code field. an 11-bit-wide field, encoding 2048 possible messages. unformatted code field. an 11-bit-wide field that may contain an arbitrary value. table 24: next page transmit register (address 07d, 07h) bit name r/w description default 15 next page r/w 1 = additional next page(s) follows 0 = last page 0 14 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ?? 0 13 message page r/w 1= message page 0 = unformatted page 1 12 acknowledge 2 r/w 1 = will comply with message 0 = cannot comply with message 0 11 toggle ro 1 = previous value of the transmitted link code word equalled logic 0 0 = previous value of the transmitted link code word equalled logic 1 0 10:0 message/unformatted code field r/w ? 1 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
BCM5238 advance data sheet 1/31/03 broadcom corporation page 36 100base-x auxiliary control register document 5238-ds03-405-r a uto -n egotiation l ink p artner (lp) n ext p age t ransmit r egister next page. indicates whether this is the last next page. message page. differentiates a message page from an unformatted page. acknowledge 2. indicates that the link partner has the ability to comply with the message. toggle. used by the arbitration function to ensure synchronization with the link partner during next page exchange. message code field. an 11-bit-wide field, encoding 2048 possible messages. unformatted code field. an 11-bit-wide field that may contain an arbitrary value. 100base-x a uxiliary c ontrol r egister table 25: next page transmit register (address 08d, 08h) bit name r/w description default 15 next page ro 1 = additional next page(s) follows 0 = last page 0 14 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ?? 0 13 message page ro 1= message page 0 = unformatted page 0 12 acknowledge 2 ro 1 = will comply with message 0 = cannot comply with message 0 11 toggle ro 1 = previous value of the transmitted link code word equalled logic 0 0 = previous value of the transmitted link code word equalled logic 1 0 10:0 message/unformatted code field ro ? 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). table 26: 100-base-x auxiliary control register (address 16d, 10h) bit name r/w description default 15:14 reserved a ?? 0 13 transmit disable r/w 1 = transmitter disabled in phy 0 = normal operation 0 12 reserved a ?? 0 11 reserved a ?? 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r 100base-x auxiliary control register page 37 transmit disable. the transmitter may be disabled by writing a 1 to bit 13 of mii register 10h. the transmitter output (td) is forced into a high impedance state. bypass 4b5b encoder/decoder. the 4b5b encoder and decoder may be bypassed by writing a 1 to bit 10 of mii register 10h. the transmitter sends 5b codes from the txer and txd signals directly to the scrambler. txen must be active and frame encapsulation (insertion of j/k and t/r codes) is not performed. the receiver places descrambled and aligned 5b codes onto the rxer and rxd signals. crs is asserted when a valid frame is received. bypass scrambler/descrambler. the stream cipher function may be disabled by writing a 1 to bit 9 of mii register 10h. the stream cipher function may be reenabled by writing a 0 to this bit. bypass nrzi encoder/decoder. the nrzi encoder and decoder can be bypassed by writing a 1 to bit 8 of mii register 10h, causing 3-level nrz data to be transmitted and received on the cable. normal operation (3-level nrzi encoding and decoding) may be re-enabled by writing a 0to this bit. bypass receive symbol alignment. receive symbol alignment may be bypassed by writing a 1 to bit 7 of mii register 10h. when used in conjunction with the bypass 4b5b encoder/decoder bit, unaligned 5b codes are placed directly on the rxer and rxd signals. baseline wander correction disable. the baseline wander correction circuit may be disabled by writing a 1 to bit 6 of mii register 10h. the BCM5238 corrects for baseline wander on the receive data signal when this bit is cleared. extended fifo enable. controls the extended receive fifo mechanism. this bit may have to be set if the jumbo packet enable bit is set. see table 3 on page 17 for details. 10 bypass 4b5b encoder/decoder r/w 1 = transmit and receive 5b codes over smii pins 0 = normal smii interface 0 9 bypass scrambler/descrambler r/w 1 = scrambler and descrambler disabled 0 = scrambler and descrambler enabled 0 8 bypass nrzi encoder/decoder r/w 1 = nrzi encoder and decoder is disabled 0 = nrzi encoder and decoder is enabled 0 7 bypass receive symbol alignment r/w 1 = 5b receive symbols not aligned 0 = receive symbols aligned to 5b boundaries 0 6 baseline wander correction disable r/w 1 = baseline wander correction disabled 0 = baseline wander correction enabled 0 5 fef enable r/w 1 = far end fault enabled 0 = far end fault disabled 0 4:3 reserved a ?? 0 2 extended fifo enable r/w 1 = extended fifo mode, 0 = normal fifo mode 0 1:00 reserved a ?? 00 a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. table 26: 100-base-x auxiliary control register (address 16d, 10h) (cont.) bit name r/w description default note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
BCM5238 advance data sheet 1/31/03 broadcom corporation page 38 100base-x auxiliary status register document 5238-ds03-405-r 100base-x a uxiliary s tatus r egister smii overrun/underrun error. the phy returns a 1 in bit 11, when the smii receive fifo encounters an overrun or underrun condition. locked. the phy returns a 1 in bit 9 when the de-scrambler is locked to the incoming data stream. otherwise, it returns a 0. current 100base-x link status. the phy returns a 1 in bit 8 when the 100base-x link status is good. otherwise, it returns a 0. remote fault. the phy returns a 1 while its link partner is signalling a far-end fault condition. otherwise, it returns a 0. false carrier detected. the phy returns a 1 in bit 5 of the extended status register if a false carrier has been detected since the last time this register was read. otherwise, it returns a 0. bad esd detected. the phy returns a 1 in bit 4 if an end-of-stream delimiter error has been detected since the last time this register was read. otherwise, it returns a 0. receive error detected. the phy returns a 1 in bit 3 if a packet was received with an invalid code since the last time this register was read. otherwise, it returns a 0. table 27: 100base-x auxiliary status register (address 17d, 11h) bit name r/w description default 15:12 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ?? 0 11 smii overrun/underrun detected ro 1 = error detected 0 = no error 0 10 reserved a ?? pin 9 locked ro 1 = descrambler locked 0 = descrambler unlocked 0 8 current 100base-x link status ro 1 = link pass 0 = link fail 0 7 remote fault ro 1 = remote fault detected 0 = no remote fault detected 0 6 reserved a ?? 0 5 false carrier detected ro lh 1 = false carrier detected since last read 0 = no false carrier since last read 0 4 bad esd detected ro lh 1 = esd error detected since last read 0 = no esd error since last read 0 3 receive error detected ro lh 1 = receive error detected since last read 0 = no receive error since last read 0 2 transmit error detected ro lh 1 = transmit error code received since last read 0 = no transmit error code received since last read 0 1 lock error detected ro lh 1 = lock error detected since last read 0 = no lock error since last read 0 0 mlt3 code error detected ro lh 1 = mlt3 code error detected since last read 0 = no mlt3 code error since last read 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r 100base-x receive error counter page 39 transmit error detected. the phy returns a 1 in bit 2 if a packet was received with a transmit error code since the last time this register was read. otherwise, it returns a 0. lock error detected. the phy returns a 1 in bit 1 if the descrambler has lost lock since the last time this register was read. otherwise, it returns a 0. mlt3 code error detected. the phy returns a 1 in bit 0 if an mlt3 coding error has been detected in the receive data stream since the last time this register was read. otherwise, it returns a 0. 100base-x r eceive e rror c ounter receive error counter [15:0]. this counter increments each time the BCM5238 receives a noncollision packet containing at least one receive error. the counter automatically clears itself when read. when the counter reaches its maximum value, ffh, it stops counting receive errors until cleared 100base-x f alse c arrier s ense c ounter overrun/underrun counter [7:0]. the overrun/underrun counter increments each time the BCM5238 detects an overrun or underrun of the receive fifos. the counter automatically clears itself when read. when the counter reaches its maximum value, ffh, it stops counting overrun/underrun errors until cleared. false carrier sense counter [7:0]. this counter increments each time the BCM5238 detects a false carrier on the receive input. this counter automatically clears itself when read. when the counter reaches its maximum value, ffh, it stops counting false carrier sense errors until cleared. table 28: 100base-x receive er ror counter (address 18d, 12h) bit name r/w description default 15:0 receive error counter [15:0] r/w number of noncollision packets with receive errors since last read 0000h table 29: 100base-x false carrier sense counter (address 19d, 13h) bit name r/w description default 15:8 smii overrun/underrun counter [7:0] r/w number of overruns/underruns since last read 00h 7:0 false carrier sense counter [7:0] r/w number of false carrier sense events since last read 00h
BCM5238 advance data sheet 1/31/03 broadcom corporation page 40 auxiliary control/status register document 5238-ds03-405-r 100base-x d isconnect c ounter smii fast rxd. extended fifo operation only. bit 15 of the disconnect counter register indicates the fifo state machine has detected fast receive data relative to the ref_clk input. smii slow rxd. extended fifo operation only. bit 14 of the disconnect counter register indicates the fifo state machine has detected slow receive data relative to the ref_clk input. a uxiliary c ontrol /s tatus r egister table 30: 100base-x disconnect counter (address 20d, 14h) bit name r/w description default 15 smii fast rxd r/o 1 = in extended fifo mode, detect fast receive data 0 = normal 0 14 smii slow rxd r/o 0 = normal 1 = in extended fifo mode, detect slow receive data 0 13:8 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ? ? 000010 7:0 reserved a ?? 00h note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). table 31: auxiliary control/status register (address 24d, 18h) bit name r/w description default 15 jabber disable r/w 1= jabber function disabled in phy 0 = jabber function enabled in phy 0 14 link disable r/w 1= link integrity test disabled in phy 0 = link integrity test is enabled in phy 0 13:8 reserved a ? ? 000000 7:6 hsq : lsq r/w these two bits define the squelch mode of the 10base-t carrier sense mechanism: 00 = normal squelch 01 = low squelch 10 = high squelch 11 = not allowed 00 5:4 edge rate [1:0] r/w 00 = 1 nanoseconds 01 = 2 nanoseconds 10 = 3 nanoseconds 11 = 4 nanoseconds 11 3 auto-negotiation indicator ro 1 = auto-negotiation activated 0 = speed forced manually 1 2 force 100/10 indication ro 1 = speed forced to 100base-x 0 = speed forced to 10base-t 1 1 speed indication ro 1 = 100base-x 0 = 10base-t 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r auxiliary control/status register page 41 jabber disable. 10base-t operation only. bit 15 of the auxiliary contro l register allows the user to disable the jabber detect function, defined in the ieee standard. this function shuts off the transmitter when a transmission request has exceeded a maximum time limit. by writing a 1 to bit 15 of the auxiliary control register, the jabber detect function is disabled. writing a 0 to this bit or resetting the chip restores normal operation. reading this bit returns the value of jabber detect disable. link disable. writing a 1 to bit 14 of the auxiliary control register allo ws the user to disable the link integrity state machines, and place the bcm5248 into forced link pass status. writing a 0 to this bit or resetting the chip restores the link integrity functions. reading this bit returns the value of link integrity disable. hsq:lsq. extends or decreases the squelch levels for detection of incoming 10base-t data packets. the default squelch levels implemented are those defined in the ieee standard. the high-squelch and low-squelch levels are useful for situations where the ieee-prescribed levels are inadequate. the squelch levels are used by the crs/link block to filter out noise and recognize only valid packet preambles and link integrity pulses. extending the squelch levels allows the bcm5248 to operate properly over longer cable lengths. decreasing the squelch levels may be useful in situations where there is a high level of noise present on the cables. reading these two bits returns the value of the squelch levels. edge rate [1:0]. control bits used to program the transmit dac output edge rate in 100base-tx mode. these bits are logically anded with the er[1:0] input pins to produce the internal edge-rate controls (edge_rate[1] and er[1], edge_rate[0] and er[0]). auto-negotiation indicator. a read-only bit that indicates whether auto-negotiation has been enabled or disabled on the bcm5248 . a combination of a 1 in bit 12 of the control register and a logic 1 on the anen input pin is required to enable auto-negotiation. when auto-negotiation is disabled, bit 3 of the auxiliary control register returns a 0. at all other times, i t returns a 1. force100/10 indication. a read-only bit that returns a value of 0 when one of following two cases is true: the anen pin is low and the f100 pin is low bit 12 of the control register has been written as 0 and bit 13 of the control register has been written as 0. when bit 8 of the auxiliary control register is 0, the speed of the chip is 10base-t. in all other cases, either the speed is not forced (auto-negotiation is enabled), or the speed is forced to 100base-x. speed indication. bit 1 of the auxiliary control register is a read-only bit that shows the true current operation speed of the bcm5248 . a 1 bit indicates 100base-x operation, whereas a 0 indicates 10base-t operation. note that while the auto- negotiation exchange is being performed, the bcm5248 is always operating at 10base-t speed. full-duplex indication. bit 0 of the auxiliary control register is a read-only bit that returns a 1 when the BCM5238 is in full- duplex mode. in all other modes, it returns a 0. 0 full-duplex indication ro 1 = full-duplex active 0 = full-duplex not active 0 a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. table 31: auxiliary control/status register (address 24d, 18h) (cont.) bit name r/w description default note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
BCM5238 advance data sheet 1/31/03 broadcom corporation page 42 auxiliary control/status register document 5238-ds03-405-r a uxiliary s tatus s ummary r egister auxiliary status summary register contains copies of redundant status bits found elsewhere within the mii register space. descriptions for each of these individual bits can be found associated with the primary register descriptions. table 32: auxiliary status summary register (address 25d, 19h) bit name r/w description default 15 auto-negotiation complete ro 1 = auto-negotiation process completed 0 14 auto-negotiation complete acknowledge ro lh 1 = auto-negotiation completed acknowledge state 0 13 auto-negotiation acknowledge detected ro lh 1 = auto-negotiation acknowledge detected 0 12 auto-negotiation ability detect ro lh 1 = auto-negotiation for link partner ability 0 11 auto-negotiation pause ro BCM5238 and link partner pause operation bit set 0 10:8 auto-negotiation hcd ro 000 = no highest common denominator 001 = 10base-t 010 = 10base-t full-duplex 011 = 100base-tx 100 = 100base-t4 101 = 100base-tx full-duplex 11x = undefined 000 7 auto-negotiation parallel detection fault ro lh 1 = parallel detection fault 0 6 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ?? 0 5 link partner page received ro 1 = new page has been received. 0 4 link partner auto-negotiation able ro 1 = link partner is auto-negotiation capable 0 3 speed indicator ro 1 = 100 mbps 0 = 10 mbps 0 2 link status ro ll 1 = link is up (link pass state) 0 1 auto-negotiation enabled ro 1 = auto-negotiation enabled 1 0 full duplex indication ro ll 1 = full-duplex active 0 = full-duplex inactive 0 r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r auxiliary control/status register page 43 i nterrupt r egister fdx led enable. setting this bit enables fdx led mode. bit 15 and 14 of this register are mutually exclusive. when fdx led mode is enabled, transmit led becomes full-duplex led and receive led becomes activity led. interrupt enable. setting this bit enables interrupt mode. the state of this bit also affects which status signals are shifted out on the serial led data in serial led mode. see table 5 on page 18 for details. fdx mask. when this bit is set, changes in duplex mode does not generate an interrupt. spd mask. when this bit is set, changes in operating speed does not generate an interrupt. link mask. when this bit is set, changes in link status does not generate an interrupt. interrupt mask. master interrupt mask. when this bit is set, no interrupts will be generated, regardless of the state of the other mask bits. global interrupt indicator. a 1 indicates an interrupt is present within the BCM5238. fdx change. a 1 indicates a change of duplex status since last register read. register read clears the bit. spd change. a 1 indicates a change of speed status since last register read. register read clears the bit. link change. a 1 indicates a change of link status since last register read. register read clears the bit. interrupt status. represents status of the intr pin. a 1 indicates that the interrupt mask is off and that one or more of the change bits are set. register read clears the bit. table 33: interrupt register (address 26d, 1ah) bit name r/w description default 15 fdx led enable r/w ignore when read 1 14 intr enable r/w interrupt enable 0 13:12 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ?? 00 11 fdx mask r/w full-duplex interrupt mask 1 10 spd mask r/w speed interrupt mask 1 9 link mask r/w link interrupt mask 1 8 intr mask r/w master interrupt mask 1 7:5 reserved a ?? 000 4 global interrupt indicator ro 1= indicates an interrupt is present within the BCM5238 0 3 fdx change ro, lh duplex change interrupt 0 2 spd change ro, lh speed change interrupt 0 1 link change ro, lh link change interrupt 0 0 intr status ro, lh interrupt status 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
BCM5238 advance data sheet 1/31/03 broadcom corporation page 44 auxiliary control/status register document 5238-ds03-405-r a uxiliary m ode 2 r egister 10bt dribble bit correct. when enabled, the phy rounds-down to the nearest nibble when dribble bits are present on the 10base-t input stream. jumbo packet mode. when enabled, the 100base-x unlock timer changes to allow long packets. see table 4 on page 17 for details. jumbo packet fifo enable. when enabled, the receive fifo doubles from 7 nibbles to 14 nibbles. the jumbo packet fifo enable bit should be set to a 1 when jumbo packet mode is enabled. see table 3 on page 17 for details. block 10bt echo mode. when enabled, during 10base-t half-duplex transmit operation, the txen signal does not echo onto the rxdv signal. the txen echoes onto the crs signal and the crs deassertion directly follows the txen deassertion. traffic meter led mode. when enabled, the activity leds (actled and fdxled if full-duplex led and interrupt led modes are not enabled) does not blink based on the internal led clock (approximately 80 ms on time). instead, they blink based on the rate of receive and transmit activity. each time a receive or transmit operation occurs, the led turns on for a minimum of 5 ms. during light traffic, the led blinks at a low rate, while during heavier traffic the leds remain on. serial led mode. when enabled, normal serial led mode is enabled. serial led mode can also be enabled through hardware during power-on reset. note that this bit is available only in phy 1 of 8. this bit in all other phys are reserved. activity led force on. when asserted, the activity leds (actled and fdxled if full-duplex led and interrupt led modes are not enabled) are turned on. this bit has a higher priority than the activity led force inactive, bit 4, register 1dh. table 34: auxiliary mode 2 register (address 27d, 1bh) bit name r/w description default 15:12 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ?? 0 11 10bt dribble bit correct r/w 1 = enable, 0 = disable 0 10 jumbo packet mode r/w 1 = enable, 0 = disable 0 9 jumbo packet fifo enable r/w 1 = enable, 0 = disable 0 8 reserved a ?? 0 7 block 10bt echo mode r/w 1 = enable, 0 = disable 1 6 traffic meter led mode r/w 1 = enable, 0 = disable 0 5 activity led force on r/w 1 = on, 0 = normal operation 0 4 serial led mode (this bit is available only in phy 1 of 8) r/w 1 = enable serial led mode 0 3 reserved a ?? 1 2 activity/link led mode r/w 1 = enable, 0 = disable 0 1 qual parallel detect mode r/w 1 = enable, 0 = disable 1 0 reserved a ?? 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r 10base-t auxiliary error and general status register page 45 activity/link led mode. when enabled, the receive output goes active upon acquiring link and pulses during receive or transmit activity, otherwise known as blinking link led. qualified parallel detect mode. this bit allows the auto-negotiation/parallel-detection process to be qualified with information in the advertisement register. if this bit is not set, the local BCM5238 device is enabled to auto-negotiate, and the far-end device is a 10base-t or 100base-x non-auto-negotiating legacy type, the local device will auto-negotiate/parallel-detect the far-end device, regardless of the contents of its advertisement register (04h). if this bit is set, the local device compares the link speed detected to the contents of its advertisement register. if the particular link speed is enabled in the advertisement register, the local device asserts link. if the link speed is disabled in this register, then the local device does not assert link, and continues monitoring for a matching capability link speed. 10base-t a uxiliary e rror and g eneral s tatus r egister mdix status. this bit, when read as a 1, indicates that the mdi td and rd signals for the BCM5238 have been swapped. the cause for this is one of the following: table 35: 10base-t auxiliary error and general status register (address 28d, 1ch) bit name r/w description default 15:14 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ?? 0 13 mdix status ro 0 = mdi is in use 1 = mdix is in use 0 12 mdix manual swap rw 0 = mdi or mdix if mdix is not disabled 1 = force mdix 0 11 hp auto-mdix disable r/w 0 = enable hp auto-mdix 1 = disable hp auto-mdix 0 10 manchester code error ro 1 = manchester code error (10base-t) 0 9 end of frame error ro 1 = eof detection error (10base-t) 0 8 reserved a ?? 0 7:5 reserved a ?? 001 4 reserved a ?? 0 3 auto-negotiation indication ro 1 = auto-negotiation activated 0 = speed forced manually 1 2 force 100/10 indication ro 1 = speed forced to 100base-x 0 = speed forced to 10base-t 1 1 speed indication ro 1 = 100base-x 0 = 10base-t 0 0 full-duplex indication ro 1 = full-duplex active 0 = full-duplex not active 0 note: all error bits in the auxiliary error and general status register are read-only and are latched high. when certain types of errors occur in the bcm5248 , one or more corresponding error bits become 1. they remain so until the register is read, or until a chip reset occurs. all such errors necessarily result in data errors, and are indicated by a high value on the rxer signal at the time the error occurs. note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
BCM5238 advance data sheet 1/31/03 broadcom corporation page 46 auxiliary mode register document 5238-ds03-405-r the mdix swap bit was manually set to a 1, or the hp auto-mdix function is enabled and the BCM5238 has detected an mdi cross-over cable. mdix manual swap. when this bit is set to a 1, the mdi td and rd signals for the BCM5238 are forced into being swapped. hp auto-mdix disable. when this bit is set to a 1, the hp auto-mdix function is disabled in the BCM5238. manchester code error. indicates that a manchester code violation was received. this bit is only valid during 10base-t operation. end of frame error. indicates that the end-of-frame (eof) sequence was improperly received, or not received at all. this error bit is only valid during 10base-t operation. auto-negotiation indication. a read-only bit that indicates whether auto-negotiation has been enabled or disabled on the bcm5248 . a combination of a 1 in bit 12 of the control register and a logic 1 on the anen input pin is required to enable auto-negotiation. when auto-negotiation is disabled, bit 15 of the auxiliary mode register returns a 0. at all other times, it returns a 1. force 100/10 indication. a read-only bit that returns a value of 0 when one of following two cases is true: the anen pin is low and the f100 pin is low, or bit 12 of the control register has been written 0 and bit 13 of the control register has been written 0. when bit 2 of the auxiliary control register is 0, the speed of the chip is 10base-t. in all other cases, either the speed is not forced (auto-negotiation is enabled), or the speed is forced to 100base-x. speed indication. a read-only bit that shows the true current operation speed of the bcm5248 . a 1 bit indicates 100base-x operation, whereas a 0 indicates 10base-t operat ion. note that while the auto-negotiation exchange is performed, the bcm5248 is always operating at 10base-t speed. full-duplex indication. a read-only bit that returns a 1 when the bcm5248 is in full-duplex mode. in all other modes, it returns a 0. a uxiliary m ode r egister table 36: auxiliary mode register (address 29d, 1dh) bit name r/w description default 15:5 reserved a ? ? 000h 4 activity led disable r/w 1 = disable xmt/rcv activity led outputs 0 = enable xmt/rcv activity led outputs 0 3 link led disable r/w 1 = disable link led output 0 = enable link led output 0 2 reserved a ?? 0 1 block txen mode r/w 1 = enable block txen mode 0 = disable block txen mode 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r auxiliary multiple phy register page 47 activity led disable. when set to 1, disables the actled output pin. when 0, actled output pin is enabled. link led disable. when set to 1, disables the link led output pin. when 0, link led output is enabled. block txen mode. when this mode is enabled, short ipgs of 1, 2, 3 or 4 txc cycles all result in the insertion of two idles before the beginning of the next packet?s jk symbols. a uxiliary m ultiple phy r egister hcd bits. bits 15:11 of the auxiliary multiple phy register are five read-only bits that report the highest common denominator (hcd) result of the auto-negotiation process. immediately upon entering the link pass state after each reset or restart auto-negotiation, only one of these five bits will be 1. the link pass state is identified by a 1 in bit 6 or 7 of t his register. the hcd bits are reset to 0 every time auto-negotiation is restarted or the BCM5238 is reset. note that for their intended application, these bits uniquely identify the hcd only a fter the first link pass after reset or restart of auto- 0 reserved a ?? 0 a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. table 37: auxiliary multiple phy register (address 30d, 1eh) bit name r/w description default 15 hcd_tx_fdx ro 1 = auto-negotiation result is 100base-tx full-duplex 0 14 hcd_t4 ro 1 = auto-negotiation result is 100base-t4 0 13 hcd_tx ro 1 = auto-negotiation result is 100base-tx 0 12 hcd_10base-t_fdx ro 1 = auto-negotiation result is 10base-t full-duplex 0 11 hcd_10base-t ro 1 = auto-negotiation result is 10base-t 0 10:9 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ?? 00 8 restart auto-negotiation r/w (sc) 1 = restart auto-negotiation process 0 = (no effect) 0 7 auto-negotiation complete ro 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 0 6 acknowledge complete ro 1 = auto-negotiation acknowledge completed 0 5 acknowledge detected ro 1 = auto-negotiation acknowledge detected 0 4 ability detect ro 1 = auto-negotiation waiting for lp ability 0 3 super isolate r/w 1 = super isolate mode 0 = normal operation 0 2 reserved a ?? 0 1 10base-t serial mode r/w 1 = enable 10base-t serial mode 0 = disable 10base-t serial mode 0 0 reserved a ?? 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). table 36: auxiliary mode register (address 29d, 1dh) (cont.) bit name r/w description default note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
BCM5238 advance data sheet 1/31/03 broadcom corporation page 48 broadcom test register document 5238-ds03-405-r negotiation. on later link fault and subsequent renegotiations, if the ability of the link partner is different, more than one of the above bits may be active. restart auto-negotiation. a self-clearing bit that allows the auto-negotia tion process to be restar ted, regardless of the current status of the state machine. for this bit to work, auto-negotiation must be enabled. writing a 1 to this bit restarts a uto- negotiation. since the bit is self-clearing, it always returns a 0 when read. the operation of this bit is identical to bit 9 o f the control register. auto-negotiation complete. this read-only bit returns a 1 after the auto-negotiation process has been completed. it remains 1 until the auto-negotiation process is restarted, a link fault occurs, or the chip is reset. if auto-negotiation is di sabled or the process is still in progress, the bit returns a 0. acknowledge complete. this read-only bit returns a 1 after the acknowledgment exchange portion of the auto-negotiation process has been completed and the arbitrator state machine has exited the acknowledge complete state. it remains this value until the auto-negotiation process is restarted, a link fault occurs, auto-negotiation is disabled, or the BCM5238 is res et. acknowledge detected. this read-only bit is set to 1 when the arbitrator state machine exits the acknowledge detected state. it remains high until the auto-negotiation process is restarted, or the BCM5238 is reset. ability detect. this read-only bit returns a 1 when the auto-negotiation state machine is in the ability detect state. it enters this state a specified time period after the auto-negotiation process begins, and exits after the first flp burst or link pulse s are detected from the link partner. this bit returns a 0 any time the auto-negotiation state machine is not in the ability dete ct state. super isolate. writing a 1 to this bit places the bcm5248 into the super isolate mode. similar to the isolate mode, all txd0{n} inputs are ignored, and all rxd0{n}i outputs are tri-stated. additionally, all link pulses are suppressed. this allows the bcm5248 to coexist with another phy on the same adapter card, with only one being activated at any time. 10base-t serial mode. writing a 1 to bit 1 of the auxiliary mode register enables the 10base-t serial mode. serial operation is not available in 100base-x mode. b roadcom t est r egister table 38: broadcom test register (address 31d, 1fh) bit name r/w description default 15:8 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ?? 00h 7 shadow register enable r/w 1 = enable shadow registers 18h?1eh 0 = disable shadow registers 0 6 reserved a ?? 0 5 reserved a ?? 0 4:0 reserved a ?? 0bh note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r auxiliary mode 4 (phy 1 of 8) register (shadow register) page 49 shadow register enable. writing a 1 to bit 7 of register 1fh allows r/w access to the shadow registers located at addresses 1ah?1eh. a uxiliary m ode 4 (phy 1 of 8) r egister (s hadow r egister ) mii led select enable. default parallel mode configuration of led1 and led2 through mii register writes is enabled when this bit is set to a 1. otherwise, power-on reset configurations are in effect (for details of all available configurations, se e ?led display output modes? on page 18 ). a uxiliary m ode 4 (phy 2 of 8) r egister (s hadow r egister ) table 39: auxiliary mode 4 (phy 1 of 8) register (shadow register 26d, 1ah) bit name r/w description default 15:10 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ? ? 001100 9 mii led select enable r/w 1 = enable led output selection through mii register 0 8:6 reserved a ?? 0 5:3 parallel led2/ extended led2 for phy 1 of 8 select[2:0] r/w configuration bits for led2 output (see ?led display output modes? on page 18 for details) 0 2:0 parallel led1/ extended led1 for phy 1 of 8 select[2:0] r/w configuration bits for led1 output (see ?led display output modes? on page 18 for details) 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1. table 40: auxiliary mode 4 (phy 2 of 8) register (shadow register 26d, 1ah) bit name r/w description default 15:10 reserved a ? ? 001100 9 serial led program enable r/w 1 = enable normal serial led programming. 0 = default serial led is active when serial led is enabled (see ?led display output modes? on page 18 for details) 0 8:6 reserved a ?? 000 5:3 serial led bank 6/ extended led2 for phy 2 of 8 select[2:0] r/w configuration bits for serial led bank 6 and led2 output for phy 2 of 8 (see ?led display output modes? on page 18 for details) 000 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1.
BCM5238 advance data sheet 1/31/03 broadcom corporation page 50 auxiliary mode 4 (phy 3 of 8) register (shadow register) document 5238-ds03-405-r serial led program enable. when this bit is set, then serial led mode bit stream and its values can be configured (for details of all available configurations, see ?led display output modes? on page 18 ). a uxiliary m ode 4 (phy 3 of 8) r egister (s hadow r egister ) extended led enable. when this bit is set, then extended parallel led mode is selected. in this mode, led1 and led2 each phy can be individually programmed to output-specific led status (for details of all available configurations, see ?led display output modes? on page 18 ). 2:0 serial led bank 5/ extended led1 for phy 2 of 8 select[2:0] r/w configuration bits for serial led bank 5 and led1 output for phy 2 of 8 (see ?led display output modes? on page 18 for details) 000 a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. table 41: auxiliary mode 4 (phy 3 of 8) register (shadow register 26d, 1ah) bit name r/w description default 15:10 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ? ? 001100 9 extended led enable r/w 1 = enable extended parallel led. 0 = default parallel led is active if parallel led is active (see ?led display output modes? on page 18 for details) 0 8:6 reserved a ?? 000 5:3 serial led bank 4/ extended led2 for phy 3 of 8 select[2:0] r/w configuration bits for serial led bank 4 and led2 output for phy 3 of 8 (see ?led display output modes? on page 18 for details) 000 2:0 serial led bank 3/ extended led1 for phy 3 of 8 select[2:0] r/w configuration bits for serial led bank 3 and led1 output for phy 3 of 8 (see ?led display output modes? on page 18 for details) 000 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1. table 40: auxiliary mode 4 (phy 2 of 8) register (shadow register 26d, 1ah) bit name r/w description default note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1.
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r auxiliary mode 4 (phy 5 of 8) register (shadow register) page 51 a uxiliary m ode 4 (phy 4 of 8) r egister (s hadow r egister ) see ?led display output modes? on page 18 for details of all available configuration. a uxiliary m ode 4 (phy 5 of 8) r egister (s hadow r egister ) see ?led display output modes? on page 18 for details of all available configuration. table 42: auxiliary mode 4 (phy 4 of 8) register (shadow register 26d, 1ah) bit name r/w description default 15:6 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ? ? 00110 00000 5:3 serial led bank 2/extended led2 for phy 4 of 8 select[2:0] r/w configuration bits for serial led bank 2 and led2 output for phy 4 of 8 (see ?led display output modes? on page 18 for details) 000 2:0 serial led bank 1/extended led1 for phy 4 of 8 select[2:0] r/w configuration bits for serial led bank 1 and led1 output for phy 4 of 8 (see ?led display output modes? on page 18 for details) 000 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1. table 43: auxiliary mode 4 (phy 5 of 8) register (shadow register 26d, 1ah) bit name r/w description default 15:6 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ? ? 00110 00000 5:3 extended led2 for phy 5 of 8 select[2:0] r/w configuration bits for led2 output for phy 5 of 8 (see ?led display output modes? on page 18 for details) 000 2:0 extended led1 for phy 5 of 8 select[2:0] r/w configuration bits for led1 output for phy 5 of 8 (see ?led display output modes? on page 18 for details) 000 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1.
BCM5238 advance data sheet 1/31/03 broadcom corporation page 52 auxiliary mode 4 (phy 7 of 8) register (shadow register) document 5238-ds03-405-r a uxiliary m ode 4 (phy 6 of 8) r egister (s hadow r egister ) see ?led display output modes? on page 18 for details of all available configuration. a uxiliary m ode 4 (phy 7 of 8) r egister (s hadow r egister ) see ?led display output modes? on page 18 for details of all available configuration. table 44: auxiliary mode 4 (phy 6 of 8) register (shadow register 26d, 1ah) bit name r/w description default 15:6 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ? ? 00110 00000 5:3 extended led2 for phy 6 of 8 select[2:0] r/w configuration bits for led2 output for phy 6 of 8 (see ?led display output modes? on page 18 for details) 000 2:0 extended led1 for phy 6 of 8 select[2:0] r/w configuration bits for led1 output for phy 6 of 8 (see ?led display output modes? on page 18 for details) 000 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1. table 45: auxiliary mode 4 (phy 7 of 8) register (shadow register 26d, 1ah) bit name r/w description default 15:6 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ? ? 00110 00000 5:3 extended led2 for phy 7 of 8 select[2:0] r/w configuration bits for led2 output for phy 7 of 8 (see ?led display output modes? on page 18 for details) 000 2:0 extended led1 for phy 7 of 8 select[2:0] r/w configuration bits for led1 output for phy 7 of 8 (see ?led display output modes? on page 18 for details) 000 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1.
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r auxiliary status 2 register (shadow register) page 53 a uxiliary m ode 4 (phy 8 of 8) r egister (s hadow r egister ) see ?led display output modes? on page 18 for details of all available configuration. a uxiliary s tatus 2 r egister (s hadow r egister ) mlt3 detected. the BCM5238 returns a 1 in this bit whenever mlt3 signaling is detected. cable length 100x[2:0]. the BCM5238 provides the cable length for each port when a 100-tx link is established. table 46: auxiliary mode 4 (phy 8 of 8) register (shadow register 26d, 1ah) bit name r/w description default 15:6 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ? ? 00110 00000 5:3 extended led2 for phy 8 of 8 select[2:0] r/w configuration bits for led2 output for phy 8 of 8 (see ?led display output modes? on page 18 for details) 0 2:0 extended led1 for phy 8 of 8 select[2:0] r/w configuration bits for led1 output for phy 8 of 8 (see ?led display output modes? on page 18 for details) 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1. table 47: auxiliary status 2 register (shadow register 27d, 1bh) bit name r/w description default 15 mlt3 detected r/o 1 = mlt3 detected 0h 14:12 cable length 100x[2:0] r/o the BCM5238 shows the cable length in 20-meter increments as shown in table 48 . 000 11:6 adc peak amplitude[5:0] r/o a to d peak amplitude seen 00h 5 apd enable r/w 0 = normal mode 1 = enable auto power-down mode 0 4 apd sleep timer r/w 0 = 2.5-second sleep before wake up 1= 5.0-second sleep before wake up 0 3:0 apd wake-up timer[3:0] r/w duration of wake up 0001 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1. table 48: 100-tx port cable length cable length 100x[2:0] cable length in meters 000 < 20 001 20 to < 40 010 40 to < 60
BCM5238 advance data sheet 1/31/03 broadcom corporation page 54 auxiliary status 3 register (shadow register) document 5238-ds03-405-r adc peak amplitude[5:0]. the BCM5238 returns the 6-bit peak amplitude of the adc seen during this link. apd enable . when in normal mode, if this bit is set to a 1, the BCM5238 enters auto power-down mode. if this bit is set and the link is lost, the BCM5238 enters low power-down mode. when energy is detected, the device enters full power mode. otherwise, it wakes up after either 2.5 seconds or 5.0 seconds, as determined by the apd sleep timer bit. when the BCM5238 wakes up, it sends link pulses and also monitors energy. if the link partner?s energy is detected, the BCM5238 device continues to stay in wake-up mode for a duration determined by the apd wake-up timer before going to low power mode. apd sleep timer . this bit determines how long the BCM5238 stays in low power mode before waking up. if this bit is a 0, the BCM5238 device waits approximately 2.5 seconds before waking up. otherwise, it wakes up after approximately 5.0 seconds. apd wake-up timer[3:0] . this counter determines how long the BCM5238 stays in wake-up mode before going to low power mode. this value is specified in 40-millisecond increments from 0 to 600 milliseconds. a value of 0 forces the BCM5238 to stay in low power mode indefinitely. in this case, the BCM5238 requires a hard reset to return to normal mode. a uxiliary s tatus 3 r egister (s hadow r egister ) noise[7:0]. the BCM5238 provides the current mean-squared error value for noise when a valid link is established. fifo consumption[3:0]. the BCM5238 indicates the number of nibbles of fifo currently used. 011 60 to < 80 100 80 to < 100 101 100 to < 120 110 120 to < 140 111 > 140 table 49: auxiliary status 3 register (shadow register 28d, 1ch) bit name r/w description default 15:8 noise[7:0] r/o current mean-squared error value, valid only if link is established 00h 7:4 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ? ? 000h 3:0 fifo consumption[3:0] r/o currently utilized number of nibbles in the receive fifo 0000 note: mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1. table 48: 100-tx port cable length (cont.) cable length 100x[2:0] cable length in meters
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r auxiliary status 4 register (shadow register) page 55 a uxiliary m ode 3 r egister (s hadow r egister ) fifo size select [3:0] . the BCM5238 indicates the current selection of receive fifo size using bit 3 through 0 as shown in table 51 . the size can also be determined by bit extended fifo enable (register 10h, bit 2) and bit jumbo packet enable (register 1bh, bit 9) for backward compatibility with the 0.35 m products. a uxiliary s tatus 4 r egister (s hadow r egister ) packet length counter [15:0]. the BCM5238 shows the number of bytes in the last packet received. this is valid only when a valid link is established. table 50: auxiliary mode 3 register (shadow register 29d, 1dh) bit name r/w description default 15:4 reserved a a. when writing to this register, pres erve existing values of reserved bits by completing a read/modify write. ? ? 000h 3:0 fifo size select[3:0] r/w currently selected receive fifo size 0100 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1. table 51: current receive fifo size fifo size select[3:0] receive fifo size in use (number of bits) 0000 12 0001 16 0010 20 0011 24 0100 28 0101 32 0110 36 0111 40 1000 44 1001 48 1010 52 1011 56 1100 60 1101 64 table 52: auxiliary status 4 register (shadow register 30d, 1eh) bit name r/w description default 15:0 packet length counter[15:0] r/o number of bytes in the last received packet 0000h
BCM5238 advance data sheet 1/31/03 broadcom corporation page 56 timing and ac characteristics document 5238-ds03-405-r section 7: timing an d ac characteristics all digital output timing is specified at c l = 30 pf. output rise/fall times are measured between 10% and 90% of the output signal swing. input rise/fall times are measured between v il maximum and v ih minimum. output signal transitions are referenced to the midpoint of the output signal swing. input signal transitions are referenced to the midpoint between v il maximum and v ih minimum. figure 4: clock and reset timing when in s3mii mode, ssmii-txc, the smii source synchronous transmit clock must be running before reset rising edge. also, ssmii-txc must be frequency-locked to ref_clk. table 53: clock timing parameter symbol minimum typical maximum units ref_clk cycle time (125-mhz operation) ck_cycle 8 nanoseconds ref_clk high/low time (125-mhz operation) ck_hi ck_lo 4 nanoseconds ref_clk rise/fall time (125-mhz operation) ck_edge ? ? 1 nanoseconds table 54: reset timing parameter symbol minimum typical maximum units reset pulse length with stable ref_clk input reset_len 2 ? ? s activity after end of reset reset_wait 100 ? ? s reset rise/fall time reset_edge ? ? 10 ns ref_clk reset normal phy begin here reset_len reset_wait ck_hi ck_cycle ck_edge ck_lo ck_edge activity can reset_edge reset_edge
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r timing and ac characteristics page 57 figure 5: smii timing table 55: smii timing parameter symbol minimum typical maximum units stx setup (sclk rising) stx_setup 1.5 ns stx hold (sclk rising) stx_hold 1.0 ns sync setup (sclk rising) sync_setup 1.5 ns sync hold (sclk rising) sync_hold 1.0 ns srx delay (sclk rising) srx_delay 1.5 5.0 ns table 56: auto-negotiation timing parameter minimum typical maximum units link test pulse width 100 ns flp burst interval 5.7 16 22.3 ms clock pulse to clock pulse 111 123 139 s clock pulse to data pulse (data = 1) 55.5 62.5 69.5 s table 57: led timing parameter minimum typical maximum units led on time (actled) 80 ms led off time (actled) 80 ms table 58: mii management data interface timing parameter minimum typical maximum units mdc cycle time 40 nanoseconds sync sclk stx srx srx_delay stx_hold stx_setup sync_setup sync_hold tx_er tx_en txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 crs rx_dv rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7
BCM5238 advance data sheet 1/31/03 broadcom corporation page 58 timing and ac characteristics document 5238-ds03-405-r figure 6: management interface timing figure 7: management interface ti ming (with preamble suppression on) mdc high/low 20 nanoseconds mdc rise/fall time 10 nanoseconds mdio input setup time to mdc rising 10 nanoseconds mdio input hold time from mdc rising 10 nanoseconds mdio output delay from mdc rising 0 30 nanoseconds table 58: mii management data interface timing (cont.) parameter minimum typical maximum units mdc mdc_fall mdio_hold mdio_setup mdc_rise mdc_cycle mdio_setup mdio_hold mdio_delay mdio (into BCM5238) mdio (from BCM5238) mdc skip skip d0 d1 hi-z(external pull-up) idle s t mdio start of mdc/mdio cycle end of mdc/mdio cycle skip 2 mdc clocks between mdc/mdio cycles with preamble suppressed mii register 1, bit 6 set to 0
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r electrical characteristics page 59 section 8: electrical characteristics table 59: absolute maximum ratings symbol parameter minimum maximum units ovdd, pllvddp supply voltage gnd ? 0.3 3.465 v dvdd, avdd,pllvdd supply voltage gnd ? 0.3 1.890 v biasvdd supply voltage gnd ? 0.3 3.465 v v i input voltage gnd ? 0.3 ovdd + 0.3 v i i input current ? 10 ma t stg storage temperature ? +125 c v esd electrostatic discharge ? 1000 v note: these specifications indicate levels where permanent damage to the device may occur. functional operation is not guaranteed under these conditions. operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. table 60: recommended operating conditions symbol parameter pins mode minimum maximum units ovdd pad supply voltage ovdd ? 2.375 3.465 v dvdd digital core supply voltage dvdd ? 1.710 1.890 v avdd analog supply voltage avdd ? 1.710 1.890 v pllvddp pad pll vdd pllvddp ? 2.375 3.465 v pllvddc core pll vdd pllvddc ? 1.710 1.890 v biasvdd bias vdd biasvdd ? 2.375 3.465 v v ih high-level input voltage all digital inputs ? 2.0 v v il low-level input voltage all digital inputs ? ? 0.8 v v icm common mode input voltage rd {1:8} 100base-tx 1.85 2.05 v t a ambient operating temperature 0 70 c table 61: electrical characteristics symbol parameter pins conditions minimum typical maximum units i dd total supply current ovdd, pllvddp 100base-tx ? 20 ? ma dvdd, pllvddc 100base-tx ? 400 ? ma avdd 100base-tx ? 370 a ?ma v oh high-level output voltage digital outputs i oh = ? 12 ma, ovdd = 3.3 v ovdd ? 0.5 ? ? v digital outputs i oh = ? 12 ma, ovdd = 2.5 v ovdd ? 0.4 ? ? v td {1:8} driving loaded magnetics module ? ? vdd + 1.5 v v ol low-level output voltage all digital outputs i ol = 8 ma ? ? 0.4 v td {1:8} driving loaded magnetics module dvdd ? 1.5 ? ? v
BCM5238 advance data sheet 1/31/03 broadcom corporation page 60 electrical characteristics document 5238-ds03-405-r i i input current digital inputs w/ pull-up resistors v i = ovdd ? ? +100 a v i = dgnd ? ? ?200 a digital inputs w/ pull-down resistors v i = ovdd ? ? +200 a v i = dgnd ? ? ?100 a all other digital inputs dgnd v i ovdd ? ? 100 a i oz high-impedance output current all three-state outputs dgnd v o ovdd ? ? ? a all open-drain outputs v o = ovdd ? ? ? a v bias bias voltage rdac ? ? ? ? v a. of this value, 40 ma (per port) flows through the transformer and output stage table 61: electrical characteristics (cont.) symbol parameter pins conditions minimum typical maximum units
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r mechanical information page 61 section 9: mechanical information figure 8: 128-pin mqfp, rev. b
BCM5238 advance data sheet 1/31/03 broadcom corporation page 62 mechanical information document 5238-ds03-405-r figure 9: 256-pin fbga, rev. a
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r packaging ther mal characteristics page 63 section 10: packaging thermal characteristics theta jc for this package is 8.57c/w. the BCM5238b is designed and rated for a maximum junction temperature of 125c. theta jc for this package is 10.11c/w. the BCM5238u is designed and rated for a maximum junction temperature of 125c. table 62: theta ja vs. airflow for the BCM5238b package airflow (feet per minute) 0 100 200 400 600 theta ja (c/w) 21.73 19.56 18.61 17.96 17.28 table 63: theta ja vs. airflow for the BCM5238u package airflow (feet per minute) 0 100 200 400 600 theta ja (c/w) 23.78 21.14 20.04 18.94 18.29
BCM5238 advance data sheet 1/31/03 broadcom corporation page 64 application examples document 5238-ds03-405-r section 11: application examples figure 10: smii application figure 11: smii application using source synchronous signals BCM5238 125 mhz 16 port mac rxd{1:8} 8 8 txd{1:8} rxd{1:8} 8 8 ssync txd{1:8} BCM5238 sclk BCM5238 sclk 125 mhz 16 port mac ssync rxd{1:8} smii_rxc 8 8 smii_txc txd{1:8} smii_rsync smii_txc rxd{1:8} smii_rxc 8 8 ssync txd{1:8} smii_rsync BCM5238
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r application examples page 65 figure 12: switch application BCM5238 mac rj45 magnetics smii{7}/s3mii{7} smii{8}/s3mii{8} ref_clk leds (1) smii{2}/s3mii{2} smii{1}/s3mii td {2} rd {2} td {1} rd {1} td {7} rd {7} td {8} rd {8} 125 mhz (smii) mac mac mac rj45 (2) rj45 (7) rj45 (8)
BCM5238 advance data sheet 1/31/03 broadcom corporation page 66 ordering information document 5238-ds03-405-r section 12: ordering information part number package ambient temperature BCM5238ua3kqm 128 mqfp 0 c to 70 c (32 f to 158 f) BCM5238ba3kfb 256 fbga 0 c to 70 c (32 f to 158 f)
advance data sheet BCM5238 1/31/03 broadcom corporation document 5238-ds03-405-r ordering information page 67
document 5238-ds03-405-r broadcom corporation 16215 alton parkway p.o. box 57013 irvine, california 92619-7013 phone: 949-450-8700 fax: 949-450-8710 broadcom ? corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, f unction, or design. information furnished by broadcom corporation is believed to be accurate and reliable. however, broadcom corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any prod uct or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. BCM5238 advance data sheet 1/31/03

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